# US 2018/0323196 A1 · Method and circuit for integrated circuit body biasing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0323196 A1 - Document ID: US20180323196A1 - Status: Published application - Kind: A1 - Application number: 16/038,705 - Filed: 2018-07-18 - Published: 2018-11-08 - Earliest claimed: 2016-11-07 - Assignees: STMicroelectronics S.r.l.; STMicroelectronics (Crolles 2) SAS - Applicants: STMicroelectronics SA; STMicroelectronics (Crolles 2) SAS - Inventors: Florian Cacho; Vincent Huard - Web page: https://patentgrep.com/patent/US20180323196A1 ## CPC - H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub} - G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)} - H03K 3/037: Bistable circuits - H03K 19/00315: {in field-effect transistor circuits} - H03K 19/094: using field-effect transistors - H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical - H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current} - H10D 84/0191: {Manufacturing their doped wells} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain. ## Claims ### Claim 1 An integrated circuit comprising: a plurality of circuit domains, each circuit domain including: p-type and n-type wells; a plurality of transistor devices positioned over the p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit that, in operation, detects when a slack time of at least one of the data paths in the circuit domain falls below a threshold level, and generates an output signal on an output line based on said detection; and a biasing circuit that, in operation, modifies a biasing voltage of at least one of the n-type or p-type well of the circuit domain, wherein the p-type and n-type wells in each circuit domain comprise a plurality of p-type wells electrically coupled together and a plurality of n-type wells electrically coupled together and said n-type and p-type wells extend across the plurality of circuit domains. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein, within each circuit domain, the biasing circuit is coupled to the output line of the monitoring circuit and modifies the biasing voltage based on said output signal. ### Claim 3 (depends on 1) The integrated circuit of claim 1, further comprising a control circuit coupled to the output lines of the monitoring circuits of the plurality of circuit domains, wherein the control circuit is configured to control the biasing circuit of each circuit domain to modify the biasing voltages based on the output signals from each monitoring circuit. ### Claim 4 (depends on 1) The integrated circuit of claim 1, wherein, within each circuit domain, the biasing circuit comprises: a well tap coupled to one of the n-type or p-type wells; and a switch having a plurality of inputs coupled to corresponding supply voltage rails, and an output coupled via the well tap to the one of the n-type or p-type wells, the switch being controlled, in operation, by said output signal to select one of the supply voltage rails to be coupled to the well tap. ### Claim 5 (depends on 1) The integrated circuit of claim 1, wherein the monitoring circuit comprises: a flip-flop having a data input coupled to the at least one data path and a clock input configured to receive a clock signal; and a logic circuit that asserts the output signal if a transition of a data signal in said at least one data path occurs within a first time period of a clock edge of said clock signal. ### Claim 6 A method comprising: in each circuit domain of a plurality of circuit domains of an integrated circuit that include a plurality of monitoring circuits, respective, and a plurality of biasing circuits, respectively, detecting, by the monitoring circuit in the circuit domain, when a slack time of at least one data path in the circuit domain falls below a threshold level and generating an output signal on an output line based on said detecting, wherein each circuit domain comprises a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; and in each circuit domain, modifying, by the biasing circuit of the circuit domain, a biasing voltage of at least one of the n-type wells and p-type wells of the circuit domain, wherein the p-type and n-type wells in each circuit domain comprise a plurality of p-type wells electrically coupled together and a plurality of n-type wells electrically coupled together and said n-type and p-type wells extend across the plurality of circuit domains. ### Claim 7 (depends on 6) The method of claim 6, wherein, within each circuit domain, the biasing circuit modifies the biasing voltage based on said output signal. ### Claim 8 (depends on 6) The method of claim 6, further comprising controlling, using a control circuit coupled to the output lines of the monitoring circuits of the plurality of circuit domains, the biasing circuit of each circuit domain to modify the biasing voltages based on the output signals from each monitoring circuit. ### Claim 9 (depends on 6) The method of claim 6, wherein, within each circuit domain, the biasing circuit comprises a well tap coupled to one of the n-type or p-type wells; and a switch having a plurality of inputs coupled to corresponding supply voltage rails, and an output coupled via the well tap to the one of the n-type or p-type wells, the method further comprising controlling the switch, by said output signal to select one of the supply voltage rails to be coupled to the well tap. ### Claim 10 (depends on 6) The method of claim 6, wherein the monitoring comprises: asserting the output signal if a transition of a data signal in the at least one data path occurs within a first time period of a clock edge of a clock signal provided to a flip-flop having a data input coupled to the at least one data path. ### Claim 11 An integrated circuit comprising: a plurality of circuit domains, each circuit domain including: p-type and n-type wells; one or more data paths positioned over the p-type and n-type wells; a monitoring circuit that, in operation, detects when a slack time of at least one of the data paths in the circuit domain falls below a threshold level, and generates an output signal on an output line based on said detection; and a biasing circuit that, in operation, modifies a biasing voltage of at least one of the n-type and p-type wells of the circuit domain based on said output signal, wherein each circuit domain comprises at least one of: a p-type well enclosing an n-type well, and an n-type well enclosing a p-type well. ### Claim 12 (depends on 11) The integrated circuit of claim 11, further comprising a control circuit coupled to the output lines of the monitoring circuits of the plurality of circuit domains, wherein the control circuit is configured to control the biasing circuit of each circuit domain to modify the biasing voltages based on the output signals from each monitoring circuit. ### Claim 13 (depends on 11) The integrated circuit of claim 11, further comprising a plurality of control circuits positioned in the circuit domains, respectively, wherein for each circuit domain, the control circuit is coupled to the output line of the monitoring circuit of the circuit domain, and is configured to control the biasing circuit of the circuit domain to modify the biasing voltage based on the output signal from the monitoring circuit of the circuit domain. ### Claim 14 (depends on 11) The integrated circuit of claim 11, wherein, within each circuit domain, the biasing circuit comprises: a well tap coupled to one of the n-type or p-type wells; and a switch having a plurality of inputs coupled to corresponding supply voltage rails, and an output coupled via the well tap to the one of the n-type or p-type wells, the switch being controlled, in operation, by said output signal to select one of the supply voltage rails to be coupled to the well tap. ### Claim 15 (depends on 11) The integrated circuit of claim 11, wherein the monitoring circuit comprises: a flip-flop having a data input coupled to the at least one data path and a clock input configured to receive a clock signal; and a logic circuit that asserts the output signal if a transition of a data signal in said at least one data path occurs within a first time period of a clock edge of said clock signal. ### Claim 16 An integrated circuit comprising: a plurality of circuit domains, each circuit domain including: p-type and n-type wells; one or more data paths positioned over the p-type and n-type wells; a monitoring circuit that, in operation, detects when a slack time of at least one of the data paths in the circuit domain falls below a threshold level, and generates an output signal on an output line based on said detection; and a biasing circuit that, in operation, modifies a biasing voltage of at least one of the n-type and p-type wells of the circuit domain based on said output signal; and an insulating strip positioned between one or more n-type wells of a first of said circuit domains and one or more n-type wells of a second of said circuit domains, and between one or more p-type wells of the first of said circuit domains and one or more p-type wells of the second of said circuit domains. ### Claim 17 (depends on 16) The integrated circuit of claim 16, further comprising a control circuit coupled to the output lines of the monitoring circuits of the plurality of circuit domains, wherein the control circuit is configured to control the biasing circuit of each circuit domain to modify the biasing voltages based on the output signals from each monitoring circuit. ### Claim 18 (depends on 16) The integrated circuit of claim 16, further comprising a plurality of control circuits positioned in the circuit domains, respectively, wherein for each circuit domain, the control circuit is coupled to the output line of the monitoring circuit of the circuit domain, and is configured to control the biasing circuit of the circuit domain to modify the biasing voltage based on the output signal from the monitoring circuit of the circuit domain. ### Claim 19 (depends on 16) The integrated circuit of claim 16, wherein, within each circuit domain, the biasing circuit comprises: a well tap coupled to one of the n-type or p-type wells; and a switch having a plurality of inputs coupled to corresponding supply voltage rails, and an output coupled via the well tap to the one of the n-type or p-type wells, the switch being controlled, in operation, by said output signal to select one of the supply voltage rails to be coupled to the well tap. ### Claim 20 (depends on 16) The integrated circuit of claim 16, wherein the monitoring circuit comprises: a flip-flop having a data input coupled to the at least one data path and a clock input configured to receive a clock signal; and a logic circuit that asserts the output signal if a transition of a data signal in said at least one data path occurs within a first time period of a clock edge of said clock signal.