# US 2018/0323192 A1 · Semiconductor structures and fabrication methods thereof

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- Number: US 2018/0323192 A1
- Document ID: US20180323192A1
- Status: Published application
- Kind: A1
- Application number: 15/968,989
- Filed: 2018-05-02
- Published: 2018-11-08
- Earliest claimed: 2017-05-03
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Yong LI
- Web page: https://patentgrep.com/patent/US20180323192A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/834: {comprising FinFETs}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/50: Isolation regions based on field-effect
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a semiconductor structure includes providing a substrate including isolation regions and a device region between adjacent isolation regions; forming a plurality of fin structures, including a first plurality of fin structures on the isolation regions and a second plurality of fin structures on the device region of the substrate; forming an isolation layer, having a top surface lower than top surfaces of the fin structures, on the substrate between adjacent fin structures; etching the first plurality of fin structures on the isolation regions after forming the isolation layer; and forming a gate structure across the second plurality of fin structures on the device region after etching the first plurality of fin structures formed on the isolation regions. The gate structure covers a portion of sidewall and top surfaces of each fin structure of the second plurality of fin structures on the device region.

## Claims

### Claim 1

A method for fabricating a semiconductor structure, comprising:
providing a substrate including: isolation regions and a device region between adjacent isolation regions;
forming a plurality of fin structures, including a first plurality of fin structures on the isolation regions and a second plurality of fin structures on the device region of the substrate;
forming an isolation layer on the substrate between adjacent fin structures, the isolation layer having a top surface lower than top surfaces of the fin structures;
etching the first plurality of fin structures on the isolation regions after forming the isolation layer; and
forming a gate structure across the second plurality of fin structures on the device region after etching the first plurality of fin structures formed on the isolation regions, the gate structure covering a portion of sidewall and top surfaces of each fin structure of the second plurality of fin structures on the device region.

### Claim 2 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein forming the isolation layer on the substrate includes:
forming an isolation material layer on the substrate to cover the top surfaces of the fin structures;
performing a planarization process on the isolation material layer to form an isolation film by removing a portion of the isolation material layer formed above the top surfaces of the fin structures; and
performing an etch-back process to remove a portion of the isolation film, wherein a remaining portion of the isolation film serves as the isolation layer.

### Claim 3 (depends on 2)

The method for fabricating the semiconductor structure according to claim 2, wherein:
during the etch-back process to remove the portion of the isolation film, a gaseous hydrofluoric acid is used to etch the portion of the isolation film.

### Claim 4 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein providing the substrate and the plurality of fin structures includes:
providing an initial substrate;
etching the initial substrate to form the substrate and a plurality of discrete initial fin structures on the substrate;
forming multiple patterned layers across the initial fin structure, wherein the patterned layers cover a portion of sidewall and top surfaces of each initial fin structure and also cover a surface of the substrate;
etching the initial fin structures using the patterned layers as an etch mask to divide each initial fin structure into a plurality of fin structures; and
removing the patterned layers.

### Claim 5 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein:
when etching the first plurality of fin structures on the isolation regions, a top portion of each fin structure in the isolation regions is removed to form a dummy fin structure.

### Claim 6 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein:
when etching the first plurality of fin structures on the isolation regions, a height of an etched amount has a ratio with respect to a height of the fin structure greater than or equal to ⅓.

### Claim 7 (depends on 6)

The method for fabricating the semiconductor structure according to claim 6, wherein:
when etching the first plurality of fin structures on the isolation regions, the height of the etched amount is approximately ⅓ to ⅔ of the height of the fin structure in the isolation regions.

### Claim 8 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein:
when etching the first plurality of fin structures on the isolation regions, each fin structure in the isolation regions is fully removed.

### Claim 9 (depends on 1)

The method for fabricating the semiconductor structure according to claim 1, wherein:
after etching the first plurality of fin structures on the isolation regions, a plurality of trenches are formed in the isolation layer of the isolation regions.

### Claim 10 (depends on 9)

The method for fabricating the semiconductor structure according to claim 9, wherein:
when forming the gate structure across the second plurality of fin structures on the device region, the gate structure is also formed in the trenches.

### Claim 11

A semiconductor structure, comprising:
a substrate, including isolation regions and a device region between adjacent isolation regions;
a plurality of fin structures, formed on the device region of the substrate; and
an isolation layer, formed on the substrate, wherein:
a top surface of the isolation layer is lower than top surfaces of the fin structures, and
a height of each fin structure exposed by the isolation layer is identical.

### Claim 12 (depends on 11)

The semiconductor structure according to claim 11, further including:
a plurality of dummy fin structures, formed on the isolation regions of the substrate, wherein a top surface of each dummy fin structure is lower than the top surface of the isolation layer.

### Claim 13 (depends on 12)

The semiconductor structure according to claim 12, further including:
a gate structure, formed on top and sidewall surfaces of the fin structures on the device region and top surfaces of dummy fin structures on the isolation regions, and also covering the isolation layer.

### Claim 14 (depends on 13)

The semiconductor structure according to claim 13, wherein the gate structure includes:
a dummy oxide layer formed on the top and the sidewall surfaces of the fin structures and also on the top surfaces of the dummy fin structures; and
a dummy gate layer formed on the dummy oxide layer and the isolation layer.

### Claim 15 (depends on 14)

The semiconductor structure according to claim 14, wherein:
the dummy oxide layer is made of SiOx or SiON; and
the dummy gate layer is made of one or more of polycrystalline silicon, SiOx, SiNx, SiON, SiC, SiCN, SiCON, and amorphous silicon.

### Claim 16 (depends on 13)

The semiconductor structure according to claim 13, wherein:
the gate structure is a metal gate structure.

### Claim 17 (depends on 11)

The semiconductor structure according to claim 11, wherein:
the substrate is made of silicon;
the plurality of discrete fin structures in the device region are made of silicon; and
the isolation layer is made of SiOx.