# US 2018/0323188 A1 · Indirect readout fet

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- Number: US 2018/0323188 A1
- Document ID: US20180323188A1
- Status: Published application
- Kind: A1
- Application number: 15/585,876
- Filed: 2017-05-03
- Published: 2018-11-08
- Earliest claimed: 2017-05-03
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Jin-Ping Han; Yulong Li; Dennis M. Newns; Paul M. Solomon; Xiao Sun
- Web page: https://patentgrep.com/patent/US20180323188A1

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10B 51/30: characterised by the memory core region
- H10B 53/30: characterised by the memory core region
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/689: {having ferroelectric layers}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

## Claims

### Claim 1

A metal-insulator-metal (MIM) capacitor structure comprising:
source and drain regions formed within a semiconductor substrate;
a first conducting layer formed over the source and drain regions;
a dielectric layer formed over the first conducting layer;
a second conducting layer formed over the dielectric layer; and
a slot defined in the second conducting layer;
wherein the slot allows modulation of a field effect transistor (FET) channel formed in the semiconductor substrate.

### Claim 2 (depends on 1)

The structure of claim 1, wherein the first conducting layer is a titanium nitride (TiN) layer.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the dielectric layer is a ferroelectric layer.

### Claim 4 (depends on 1)

The structure of claim 1, wherein pinning layers are formed on opposed ends of the slot.

### Claim 5 (depends on 1)

The structure of claim 1, wherein a width of the slot is less than a total width of the dielectric layer.

### Claim 6 (depends on 1)

The structure of claim 1, wherein the second conducting layer is a gate electrode.

### Claim 7

A metal-insulator-metal (MIM) capacitor structure comprising:
source and drain regions formed within a semiconductor substrate;
a first conducting layer formed over the source and drain regions;
a dielectric layer formed over the first conducting layer;
a second conducting layer formed over the dielectric layer;
a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer;
wherein an electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

### Claim 8 (depends on 7)

The structure of claim 7, wherein pinning layers are formed on opposed ends of the dielectric layer.

### Claim 9 (depends on 8)

The structure of claim 8, wherein the pinning layers have opposite polarization relative to each other resulting in the dielectric layer separated into two regions by a domain boundary, the two regions having opposite polarization relative to each other.

### Claim 10 (depends on 9)

The structure of claim 9, wherein the domain boundary shifts based on a voltage applied to the MIM capacitor structure.

### Claim 11 (depends on 10)

The structure of claim 10, wherein the sidewall dielectric is traverse to the FET to divide the PET channel longitudinally into two regions of varying lengths and different resistivities.

### Claim 12 (depends on 10)

The structure of claim 10, wherein the sidewall dielectric extends along the PET channel to divide a width of the FET channel into two regions.

### Claim 13 (depends on 7)

The structure of claim 7, wherein sidewall dielectric defines a high permittivity spacer.

### Claim 14 (depends on 7)

The structure of claim 7, wherein the first conducting layer is a titanium nitride (Till) layer and the dielectric layer is a ferroelectric layer,

### Claim 15

A metal-insulator-metal (MIM) capacitor structure comprising:
source and drain regions formed within a semiconductor substrate;
a first conducting layer formed over the source and drain regions;
a doped region defined between the source and drain regions;
a dielectric layer formed over the first conducting layer;
a second conducting layer formed over the dielectric layer; and
a slot defined in the second conducting layer, the slot being aligned with the doped region;
wherein the slot allows modulation of a field effect transistor (FET) channel formed in the semiconductor substrate.

### Claim 16 (depends on 15)

The structure of claim 15, wherein pinning layers are formed on opposed ends of the dielectric layer.

### Claim 17 (depends on 16)

The structure of claim 16, wherein the pinning layers have opposite polarization relative to each other resulting in the dielectric layer separated into two regions by a domain boundary, the two regions having opposite polarization relative to each other.

### Claim 18 (depends on 17)

The structure of claim 17, wherein the domain boundary shifts based on a voltage applied to the MIM capacitor structure.

### Claim 19 (depends on 18)

The structure of claim 18, wherein the sidewall dielectric is traverse to the FET to divide the FET channel longitudinally into two regions of varying lengths and different resistivities.

### Claim 20 (depends on 18)

The structure of claim 18, wherein the sidewall dielectric extends along the FET channel to divide a width of the FET channel into two regions.