# US 2018/0323186 A1 · Linearity and Lateral Isolation in a BiCMOS Process Through Counter-Doping Of Epitaxial Silicon Region

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- Number: US 2018/0323186 A1
- Document ID: US20180323186A1
- Status: Published application
- Kind: A1
- Application number: 15/588,011
- Filed: 2017-05-05
- Published: 2018-11-08
- Earliest claimed: 2017-05-05
- Assignees: Newport Fab, LLC dba Jazz Semiconductor
- Applicants: Newport Fab, LLC dba Jazz Semiconductor, Inc.
- Inventors: Kurt A. Moen; Edward J. Preisler; Paul D. Hurwitz
- Web page: https://patentgrep.com/patent/US20180323186A1

## CPC

- H10D 84/401: {Combinations of FETs or IGBTs with BJTs}
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/80: Heterojunction BJTs
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0109: {the at least one component covered by H10D12/00 or H10D30/00 being a MOS device}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 10/051: {of vertical BJTs (of heterojunction BJTs H10D10/021; of Schottky BJTs H10D10/031; of thin film BJTs H10D10/041)}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for providing improved isolation structures in a SiGe BiCMOS process are provided. In one method, an n-type epitaxial layer is grown over a p-type high-resistivity substrate. A mask covers a first region, and exposes a second region, of the epitaxial layer. A p-type impurity is implanted through the mask, counter-doping the second region to become slightly p-type. Shallow trench isolation (STI) and optional deep trench isolation (DTI) regions are formed through the counter-doped second region, thereby providing an isolation structure. The first region of the epitaxial layer forms a collector region of a heterojunction bipolar transistor. In another method, shallow trenches are etched partially into the epitaxial layer through a mask. A p-type impurity is implanted through the mask, thereby counter-doping thin exposed regions of the epitaxial layer to become slightly p-type. The shallow trenches are filled with dielectric material and a CMP process is performed to form shallow trench isolation regions.

## Claims

### Claim 1

A semiconductor structure comprising:
a semiconductor substrate having a first conductivity type;
an epitaxial region formed over the semiconductor substrate, wherein the epitaxial region has a second conductivity type, opposite the first conductivity type, and wherein the epitaxial region forms a collector region of a heterojunction bipolar transistor; and
an isolation region formed on the semiconductor substrate, wherein the isolation region includes:
one or more shallow trench isolation regions;
one or more deep trench isolation regions; and
one or more lightly doped regions of the first conductivity type, each having a sheet resistance of at least about 50 KΩ/square.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor substrate has a resistivity of at least about 500 ohm-cm.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the one or more lightly doped regions are located entirely below an upper surface of the semiconductor substrate.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the epitaxial region has a sheet resistance of about 4 KΩ/square.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the one or more deep trench isolation regions are arranged in a grid, wherein the one or more lightly doped regions are located within the grid.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, further comprising a radio frequency (RF) switch fabricated in the semiconductor substrate adjacent to the isolation region, wherein the RF switch comprises a plurality of series-connected CMOS transistors.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the heterojunction bipolar transistor is included in a power amplifier.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein there are one or more openings in the one or more shallow trench isolation regions that expose the one or more lightly doped regions of the first conductivity type.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the isolation region further comprises one or more epitaxial regions having the second conductivity type.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein each of the one or more epitaxial regions is located within in an opening in the one or more shallow trench isolation regions.

### Claim 11

A method comprising:
growing an epitaxial layer over a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the epitaxial layer has a second conductivity type, opposite the first conductivity type;
forming a mask over the epitaxial layer, wherein the mask covers a first region of the epitaxial layer and exposes a second region of the epitaxial layer;
implanting a dopant having the first conductivity type through the mask into the second region of the epitaxial layer, whereby the second region of the epitaxial layer becomes counter-doped to the first conductivity type;
forming one or more shallow trench isolation regions in the counter-doped second region of the epitaxial layer, wherein portions of the counter-doped second region of the epitaxial layer are exposed through the one or more shallow trench isolation regions, and wherein the one or more shallow trench isolation regions and the counter-doped second region of the epitaxial layer form an isolation region.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
fabricating a heterojunction bipolar transistor in a first portion of the first region of the epitaxial layer; and
fabricating a CMOS device in a second portion of the first region of the epitaxial layer, wherein the isolation region isolates the heterojunction bipolar transistor and the CMOS device.

### Claim 13 (depends on 11)

The method of claim 11, further comprising, forming one or more deep trench isolation regions that extend through the one or more shallow trench isolation regions and the counter-doped second region of the epitaxial layer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising forming the one or more deep trench isolation regions in a grid, wherein the counter-doped second region of the epitaxial layer is located within the grid.

### Claim 15 (depends on 11)

The method of claim 11, wherein the implanting is performed such that the counter-doped second region of the epitaxial layer has a sheet resistance of at least about 50 KΩ/square.

### Claim 16 (depends on 11)

The method of claim 11, further comprising fabricating a radio frequency (RF) switch in the semiconductor substrate, wherein the RF switch comprises a plurality of CMOS transistors.

### Claim 17 (depends on 11)

The method of claim 11, wherein forming the one or more shallow trench isolation regions comprises performing a chemical mechanical polishing (CMP) process that exposes portions of the counter-doped second region of the epitaxial layer through the one or more shallow trench isolation regions.

### Claim 18

A method comprising:
growing an epitaxial layer over a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the epitaxial layer has a second conductivity type, opposite the first conductivity type;
forming a mask over the epitaxial layer, wherein the mask includes openings that define locations of shallow trench isolation regions to be formed;
etching into the epitaxial layer through the openings in the mask, thereby creating a plurality of shallow trenches, wherein thinned portions of the epitaxial layer remain below the shallow trenches;
implanting a dopant having the first conductivity type through the mask into the thinned portions of the epitaxial layer, whereby the thinned portions of the epitaxial layer are counter-doped to the first conductivity type; and
filling the shallow trenches with a dielectric material, thereby forming shallow trench isolation regions.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming one or more deep trench isolation regions through the epitaxial layer.

### Claim 20 (depends on 19)

The method of claim 19, further comprising forming the one or more deep trench isolation regions in a grid, wherein the counter-doped thinned portions of the epitaxial layer are located within the grid.

### Claim 21 (depends on 18)

The method of claim 18, further comprising fabricating a heterojunction bipolar transistor in the semiconductor substrate, wherein a first region of the epitaxial layer forms a collector region of the heterojunction bipolar transistor.

### Claim 22 (depends on 21)

The method of claim 21, wherein the heterojunction bipolar transistor is included in a power amplifier.

### Claim 23 (depends on 18)

The method of claim 18, wherein the implanting is performed such that the counter-doped thinned portions of the epitaxial layer have a sheet resistance of at least about 50 KΩ/square.

### Claim 24 (depends on 18)

The method of claim 18, further comprising fabricating a radio frequency (RF) switch in the semiconductor substrate, wherein the RF switch comprises a plurality of series-connected CMOS transistors.