# US 2018/0323183 A1 · Electrostatic Discharge Protection Device

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- Number: US 2018/0323183 A1
- Document ID: US20180323183A1
- Status: Published application
- Kind: A1
- Application number: 15/584,392
- Filed: 2017-05-02
- Published: 2018-11-08
- Earliest claimed: 2017-05-02
- Assignees: Macronix International Co., Ltd.
- Applicants: Macronix International Co., Ltd.
- Inventors: Hsin-Liang Chen; Tzu-Yi Hung; Min-Hsin Wu
- Web page: https://patentgrep.com/patent/US20180323183A1

## CPC

- H10D 89/711: {using bipolar transistors as protective elements}
- H01T 4/10: having a single gap or a plurality of gaps in parallel
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H01T: SPARK GAPS; OVERVOLTAGE ARRESTERS USING SPARK GAPS; SPARKING PLUGS; CORONA DEVICES; GENERATING IONS TO BE INTRODUCED INTO NON-ENCLOSED GASES (overvoltage protection circuits H02H)

## Abstract

An electrostatic discharge protection device includes: a semiconductor substrate; an N-type doped well on the substrate, the N-type doped well including a first N+ region and a first P+ region; a P-type doped well on the substrate, the P-type doped well including a second N+ region, a third N+ region, and a second P+ region between the second N+ region and the third N+ region; and a first contact positioned above a surface of the N-type doped well between the first N+ region and the first P+ region.

## Claims

### Claim 1

An electrostatic discharge protection device comprising:
a semiconductor substrate;
a first N-type doped well and a second N-type doped well on the substrate, each of the first N-type doped well and the second N-type doped well comprising a first N+ region and a first P+ region;
a P-type doped well between the first N-type doped well and the second N-typed doped well on the substrate, the P-type doped well comprising a second N+ region, a third N+ region, and a second P+ region between the second N+ region and the third N+ region; and
a first contact and a second contact positioned above a surface of the first N-type doped well and above a surface of the second N-type doped well, respectively, between the first N+ region and the first P+ region;
a poly resistor connected between the first N-type doped well and the second N− typed doped well.

### Claim 2 (depends on 1)

The device of claim 1, further comprising an additional N-type doped well, wherein the N-typed doped well and the P-typed doped well are arranged in the additional N-type doped well.

### Claim 3 (depends on 2)

The device of claim 2, wherein the N-type doped well is separated from the P-typed doped well by the additional N-type doped well.

### Claim 4 (depends on 3)

The device of claim 3, wherein the additional N-type doped well comprises an N-type epitaxial layer, an N+ buried layer or a plurality of N+ buried layers.

### Claim 5 (depends on 1)

The device of claim 1, further comprising an oxide layer on the surface of the N-type doped well, wherein the first contact is arranged on the oxide layer.

### Claim 6 (depends on 1)

The device of claim 1, further comprising a field oxide between the first P+ region and the second N+ region.

### Claim 7 (depends on 6)

The device of claim 6, further comprising a second contact arranged on the field oxide, wherein the second contact is electrically coupled to the cathode.

### Claim 8 (depends on 7)

The device of claim 7, wherein the second contact is polysilicon or metal.

### Claim 9 (depends on 6)

The device of claim 6, wherein the field oxide is a shallow trench isolation layer.

### Claim 10 (depends on 1)

The device of claim 1, wherein the P-type doped well comprises a P+ buried layer or a P− implant layer.

### Claim 11 (depends on 1)

The device of claim 1, wherein the N-type doped well comprises an N− implanted layer.

### Claim 12 (depends on 1)

The device of claim 1, wherein the first P+ region, the N-type doped well and the second P+ region form a first transistor,
the N-type doped well, the P-type doped well and the second N+ region form a second transistor, the N-type doped well providing a first well resistance between a base of the first transistor and a collector of the second transistor, and
the N-type doped well, the P-type doped well and the third N+ region form a third transistor, the P-type doped well providing a second well resistance between an emitter of the second transistor and an emitter of the third transistor.

### Claim 13 (depends on 12)

The device of claim 12, wherein the first contact is electrically tied to an anode and to either the first N+ region or the first P+ region, and
wherein the second N+ region, the third N+ region, and the second P+ region are electrically tied to a cathode
wherein the first, second and third transistors are configured and arranged to provide conductions paths between the anode and the cathode that activate at different breakdown voltages,
wherein the first transistor is operable to turn on when a first voltage is applied to the anode, the second transistor is operable to turn on when a second voltage is applied to the anode, the third transistor is operable to turn on when a third voltage is applied to the anode, and wherein the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage.

### Claim 14

An electrostatic discharge protection circuit comprising:
a first bipolar junction transistor, wherein an emitter of the first bipolar junction transistor is electrically coupled to a base of the first bipolar junction transistor by a first resistance, and the first bipolar junction transistor is operable to turn on when a first voltage is applied to the emitter of the first bipolar junction transistor;
a second bipolar junction transistor, wherein a collector of the second bipolar junction transistor is coupled to the base of the first bipolar junction transistor by a second resistance, and the second bipolar junction transistor is operable to turn on when a second voltage is applied to the emitter of the first bipolar junction transistor, the second voltage being greater than the first voltage; and
a third bipolar junction transistor, wherein a collector and a base of the third bipolar junction transistor are tied to the collector and a base, respectively, of the second bipolar junction transistor, the base of the third bipolar junction transistor is electrically coupled to an emitter of the third bipolar junction transistor by a third resistance, and the third bipolar junction transistor is operable to turn on when a third voltage is applied to the emitter of the first bipolar junction transistor, the third voltage being greater than the second voltage.

### Claim 15 (depends on 14)

The electrostatic discharge protection circuit of claim 14, wherein the first bipolar junction transistor, the second bipolar junction transistor, and the third bipolar junction transistor are integrated within a single semiconductor substrate

### Claim 16 (depends on 14)

The electrostatic discharge protection circuit of claim 14, wherein a collector of the first bipolar junction transistor is tied to the emitter of the second bipolar junction transistor.

### Claim 17 (depends on 14)

The electrostatic discharge protection circuit of claim 14, wherein the first bipolar junction transistor is a PNP transistor, the second bipolar junction transistor is an NPN transistor, and the third bipolar junction transistor is an NPN transistor.

### Claim 18 (depends on 14)

The electrostatic discharge protection circuit of claim 14, wherein the emitter of the third bipolar junction transistor is electrically coupled to ground.

### Claim 19 (depends on 14)

The electrostatic discharge protection circuit of claim 14, wherein the base of the second bipolar junction transistor is tied to an emitter of the second bipolar junction transistor.

### Claim 20

A method of fabricating an electrostatic discharge protection device, the method comprising:
providing a substrate;
forming a first N-type well on the substrate;
forming a second N-type well and a first P-type well within the first N-type well;
forming a first N+ region and a first P+ region within the second N-type well, wherein the first N+ region and the first P+ region are spaced apart within the second N-type well;
forming a second N+ region, a second P+ region, and a third N+ region within the first P-type well, wherein the second P+ region separates the second N+ region from the third N+ region;
forming a first oxide layer, wherein the first oxide layer is between the first P+ region and the second N+ region;
forming a second oxide layer, wherein the second oxide layer is positioned between the first N+ region and the first P+ region; and
forming a contact layer on the first oxide layer and on the second oxide layer.