# US 2018/0323177 A1 · 3DIC Formation with Dies Bonded to Formed RDLs

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- Number: US 2018/0323177 A1
- Document ID: US20180323177A1
- Status: Published application
- Kind: A1
- Application number: 16/036,467
- Filed: 2018-07-16
- Published: 2018-11-08
- Earliest claimed: 2016-04-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hua Yu; Sung-Feng Yeh; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US20180323177A1

## CPC

- H10W 90/00: Package configurations
- H10P 14/46: using a liquid
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 52/403: {of conductive or resistive materials}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/90: Bond pads, in general
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/473: {containing a filler}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/66: Conductive materials thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 72/01: {Manufacture or treatment}
- H10W 72/019: {of bond pads}
- H10W 72/01904: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 74/014: {using batch processing}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/334: {Thermocompression bonding}
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

## Claims

### Claim 1

A semiconductor device comprising:
a first dielectric layer;
a first plurality of bond pads disposed in the first dielectric layer;
a first device die bonded to the first dielectric layer and the first plurality of bond pads through hybrid bonds, wherein a first surface of the first device die is bonded to surfaces of the first plurality of bond pads and the first dielectric layer, the surfaces of the first plurality of bond pads and the first dielectric layer being coplanar;
a through via adjacent the first device die, the through via being coupled to the first plurality of bond pads; and
an encapsulant surrounding the first device die and the through via.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein a height of the through via is equal to a height of the encapsulant.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the through via has a height equal to a height of the encapsulant.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a first surface of the encapsulant is coplanar with the first surface of the first device die.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a second surface of the first die opposite the first surface of the die is coplanar with a second surface of the encapsulant opposite the first surface of the encapsulant.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second dielectric layer disposed on an opposite side of the first die from the first dielectric layer;
a second plurality of bond pads disposed in the second dielectric layer;
a second device die bonded to the second dielectric layer and the second plurality of bond pads through hybrid bonds, wherein a first surface of the second device die is bonded to surfaces of the second plurality of bond pads and the second dielectric layer, the surfaces of the second plurality of bond pads and the second dielectric layer being coplanar; and
a second encapsulant surrounding the second device die.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a solder region extending from one of the bond pads of the first plurality of bond pads, wherein the encapsulant at least partially surrounds the solder region.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the solder region has a height greater than a height of the encapsulant.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a plurality of solder regions connected to the first plurality of bond pads, the plurality of solder regions being disposed on a side of the first plurality of bond pads opposite the first device die.

### Claim 10

A semiconductor device comprising:
a first dielectric layer;
a plurality of redistribution lines over the first dielectric layer;
a second dielectric layer over the plurality of redistribution lines;
a plurality of bond pads in the second dielectric layer, top surfaces of the plurality of bond pads being coplanar with a top surface of the second dielectric layer;
a device die bonded to the second dielectric layer and the plurality of bond pads, the device die having a device dielectric layer bonded to the second dielectric layer through dielectric-to-dielectric bonds, the device die further having device bond pads bonded to the plurality of bond pads through direct metal bonds; and
an encapsulant encapsulating the device die.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising electrical connections extending through the first dielectric layer, the electrical connections being electrically coupled to the plurality of redistribution lines.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, further comprising a through via extending from a bond pad of the plurality of bond pads through the encapsulant.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the through via comprises a constant composition throughout.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein a first surface of the through via distal the bond pad is coplanar with a surface of the encapsulant.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, further comprising a solder region extending from a bond pad of the first plurality of bond pads through the encapsulant.

### Claim 16

A package comprising:
a first redistribution structure, the first redistribution structure comprising:
a first plurality of redistribution lines, the first plurality of redistribution lines being located in a first plurality of dielectric layers; and
a first plurality of bond pads, the first plurality of bond pads being coupled to the first plurality of redistribution lines, the first plurality of dielectric layers comprising a first surface dielectric layer, a first surface of the first surface dielectric layer being coplanar with first surfaces of the first plurality of bond pads;
a first device die comprising:
a second plurality of bond pads bonded to the first plurality of bond pads through metal-to-metal bonding;
a second plurality of dielectric layers comprising a second surface dielectric layer, the second surface dielectric layer having a second surface coplanar with second surfaces of the second plurality bond pads, wherein the first surface dielectric layer is bonded to the second surface dielectric layer through dielectric-to-dielectric bonding; and
a second redistribution structure contacting a surface of the first device die opposite the second surface of the second surface dielectric layer, the second redistribution structure comprising:
a second plurality of redistribution lines, the second plurality of redistribution lines being located in a third plurality of dielectric layers; and
a third plurality of bond pads, the third plurality of bond pads being coupled to the second plurality of redistribution lines, the third plurality of dielectric layers comprising a third surface dielectric layer, a third surface of the third surface dielectric layer being coplanar with third surfaces of the third plurality of bond pads; and
a second device die comprising:
a fourth plurality of bond pads bonded to the third plurality of bond pads through metal-to-metal bonding; and
a fourth plurality of dielectric layers comprising a fourth surface dielectric layer, the fourth surface dielectric layer having a fourth surface coplanar with fourth surfaces of the fourth plurality bond pads, wherein the third surface dielectric layer is bonded to the fourth surface dielectric layer through dielectric-to-dielectric bonding.

### Claim 17 (depends on 16)

The package of claim 16, wherein the first plurality of bond pads and the second plurality of bond pads have distinguishable interfaces.

### Claim 18 (depends on 16)

The package of claim 16, wherein the second surface dielectric layer extends laterally beyond respective edges of the first surface dielectric layer.

### Claim 19 (depends on 16)

The package of claim 16, wherein the first surface dielectric layer is bonded to the second surface dielectric layer with respective bonds comprising O—H bonds.

### Claim 20 (depends on 16)

The package of claim 16, wherein the first device die further comprises:
a semiconductor substrate; and
through-vias penetrating through the semiconductor substrate, wherein the through-vias are electrically coupled to the second plurality of bond pads.