# US 2018/0323174 A1 · Fabrication and use of through silicon vias on double sided interconnect device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0323174 A1
- Document ID: US20180323174A1
- Status: Published application
- Kind: A1
- Application number: 15/773,514
- Filed: 2015-12-23
- Published: 2018-11-08
- Earliest claimed: 2015-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Brennen K. MUELLER; Patrick MORROW; Kimin JUN; Paul B. FISCHER; Daniel PANTUSO
- Web page: https://patentgrep.com/patent/US20180323174A1

## CPC

- H10W 90/00: Package configurations
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 90/1914: {using bonding}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/652: Cross-sectional shapes
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07554: {changes in dispositions}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/879: {Bump connectors and bond wires}
- H10W 72/90: Bond pads, in general
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/743: {having disposition changed during the connecting}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/721: {of bump connectors}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

## Claims

### Claim 1

An apparatus comprising:
a circuit structure comprising a device stratum comprising a plurality of transistor devices each comprising a first side and an opposite second side;
one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and
a substrate comprising an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels on a first side of the structure so that the one or more interconnect levels are between the through silicon via and the device stratum.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the one or more electrically conductive interconnect levels comprise one or more first interconnect levels, the apparatus further comprising one or more second interconnect levels on a second side of the device stratum coupled to ones of the transistor devices.

### Claim 3 (depends on 2)

The apparatus of claim 2, further comprising contact points disposed on the second side of the device stratum operable to be coupled to an external source and coupled to the at least second interconnect layer.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the through silicon via comprises a first side coupled to the one or more electrically conductive interconnect level and a second side operable to be coupled to an external source.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the second side of the through silicon via defines a contact pad.

### Claim 6 (depends on 4)

The apparatus of claim 4, further comprising contact pads disposed on the second side of the through silicon via operable to be coupled to an external source and coupled to the through silicon via.

### Claim 7

A system comprising:
a package substrate comprising a supply connection; and
a die coupled to the package substrate, the die comprising:
(i) a device stratum comprising a plurality of transistor devices each comprising a first side and an opposite second side;
(ii) one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and
(iii) a substrate comprising a an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect level on a first side of the structure so that the one or more interconnect levels are between the through silicon via and the device stratum.

### Claim 8 (depends on 7)

The system of claim 7, wherein the one or more electrically conductive interconnect levels comprise one or more first interconnect levels, the apparatus further comprising one or more second interconnect levels on a second side of the device stratum coupled to ones of the transistor devices.

### Claim 9 (depends on 8)

The system of claim 8, further comprising contact points disposed on the second side of the device stratum operable to be coupled to an external source and coupled to the at least second interconnect layer.

### Claim 10 (depends on 7)

The system of claim 7, wherein the through silicon via comprises a first side coupled to the one or more electrically conductive interconnect level and a second side operable to be coupled to an external source.

### Claim 11 (depends on 10)

The system of claim 10, wherein the second side of the through silicon via defines a contact pad.

### Claim 12 (depends on 10)

The system of claim 10, further comprising contact pads disposed on the second side of the through silicon via operable to be coupled to an external source and coupled to the through silicon via.

### Claim 13

A method comprising:
forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum comprising a first side and an opposite second side, wherein the second side is coupled to the substrate;
forming one or more interconnect levels on a first side of the device stratum, the one or more interconnect levels coupled to ones of the plurality of devices;
removing a portion of the substrate; and
coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

### Claim 14 (depends on 13)

The method of claim 13, wherein the through silicon via is disposed through a substrate and coupling the through silicon via to the one or more interconnect level comprises coupling the substrate comprising the through silicon via.

### Claim 15 (depends on 13)

The method of claim 13, wherein prior to coupling the through silicon via to the one or more interconnect levels, the method comprises coupling a substrate to the one or more interconnect levels and coupling the through silicon via comprises forming the through silicon via through the substrate.

### Claim 16 (depends on 13)

The method of claim 13, wherein removing a portion of the substrate comprises removing the entire portion of the substrate.

### Claim 17 (depends on 13)

The method of claim 13, wherein the one or more interconnect levels comprises a one or more first interconnect levels, the method further comprising:
forming at least one or more second interconnect levels on the second side of the device stratum wherein the one or more second interconnect levels are coupled to ones of the plurality of transistor devices.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming contact points on the second side of the device stratum operable to be coupled to an external source and coupled to the one or more second interconnect levels.

### Claim 19 (depends on 13)

The method of claim 13, wherein the through silicon vias comprise a first side coupled to the one or more interconnect level and a second side, wherein the second side of the through silicon via defines a contact pad operable to be coupled to an external source.

### Claim 20 (depends on 13)

The method of claim 13, further comprising forming contact pads on the second side of the through silicon via operable to be coupled to an external source and coupled to the through silicon via.