# US 2018/0323168 A1 · Method of manufacturing semiconductor device

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- Number: US 2018/0323168 A1
- Document ID: US20180323168A1
- Status: Published application
- Kind: A1
- Application number: 16/032,825
- Filed: 2018-07-11
- Published: 2018-11-08
- Earliest claimed: 2013-07-26
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Yoshinori MIYAKI; Masaru YAMADA
- Web page: https://patentgrep.com/patent/US20180323168A1

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10P 72/7416: {used during dicing or grinding}
- H10W 46/103: {alphanumeric information, e.g. words, letters or serial numbers}
- H10W 46/301: {for alignment}
- H10W 46/401: {for identification or tracking}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/656: Fan-in layouts
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

To enhance reliability in assembling a semiconductor device. There is provided a wiring substrate including a target mark, which is not provided on an extension line of a dicing region provided between a first semiconductor device region and a second semiconductor device region but is provided between the extension line of the dicing region and a first imaginary extension line of a first outermost peripheral land row and between the extension line of the dicing region and a second imaginary extension line of a second outermost peripheral land row. Furthermore, after mounting a semiconductor chip, wire bonding is performed, resin sealing is performed and a solder ball is mounted. After that, the dicing region is specified on the basis of the target mark, and the wiring substrate is cut along the dicing region.

## Claims

### Claim at position 1

1-7. (canceled)

### Claim 8

A method of manufacturing a semiconductor device comprising:
(a) providing a wiring substrate including:
an upper surface,
a lower surface opposite to the upper surface,
a first device region provided on the lower surface,
a second device region provided on the lower surface and also provided next to the first device region,
a dicing region provided between the first device region and the second device region
a peripheral region provided on the lower surface and also provided around the first device region, the second device region and the dicing region,
a target mark provided in the peripheral region and also not located on an extended line of the dicing region,
a plurality of first bump lands provided in a matrix, in the first device region,
a plurality of second bump lands provided in a matrix, in the second device region, and
a first insulating film formed over the lower surface such that the first insulating film exposes the plurality of first bump lands and the plurality of second bump lands,
wherein the plurality of first bump lands has a first outermost peripheral land row arranged on the outermost peripheral row of the plurality of first bump lands, which is closest to the dicing region,
wherein the plurality of second bump lands has a second outermost peripheral land row arranged on the outermost peripheral row of the plurality of second bump lands, which is closest to the dicing region,
wherein the target mark is comprised of a first pattern formed between the extended line of the dicing region and an extended line of the first outermost peripheral land row in plan view, and a second pattern formed between the extended line of the dicing region and an extended line of the second outermost peripheral land row in plan view, the first pattern and the second pattern being spaced apart from each other,
wherein a first feeder line and a second feeder line are connected to the first pattern and the second pattern, respectively,
wherein each of the first feeder line and the second feeder line has a first portion exposed from the first insulating film, and a second portion covered with the first insulating film,
wherein the first pattern, the second pattern, the first feeder line and the second feeder line are comprised of a conductive member, and
wherein a first plating film is formed on a surface of each of the first pattern exposed from the first insulating film and the second pattern exposed from the first insulating film by using the first feeder line and the second feeder line, respectively;
(b) after (a), mounting a first semiconductor chip and a second semiconductor chip on the upper surface of the wiring substrate;
(c) after (b), sealing the first semiconductor chip and the second semiconductor chip with resin;
(d) after (c), forming a plurality of first external terminals and a plurality of second external terminals on the plurality of first bump lands and the plurality of second bump lands, respectively; and
(e) after (d), identifying the dicing region on the basis of the target mark, and cutting the wiring substrate along the dicing region,
wherein, in (e), the dicing region of the wiring substrate and a first region of the peripheral region of the wiring substrate are cut off by using a rotating cutting blade, wherein the first region is located between the first pattern and the second pattern in plan view, and
wherein the first pattern, the second pattern, the first feeder line and the second feeder line are not formed in the first region.

### Claim 9 (depends on 8)

The method according to claim 8,
wherein a second insulating film is formed over the upper surface of the wiring substrate,
wherein a second plating film is formed on a surface of each of the plurality of first bump lands and the plurality of second bump lands,
wherein the second plating film is formed by using a third feeder line formed in the dicing region, and
wherein, after forming the second plating film, the third feeder line formed in the dicing region of the wiring substrate and the second insulating film covering the third feeder line are removed.

### Claim 10 (depends on 8)

The method according to claim 8,
wherein a third feeder line electrically connected with the first pattern, the second pattern, the plurality of first bump lands and the plurality of second bump lands is formed in the dicing region of the wiring substrate, and
wherein the third feeder line is covered with a second insulating film.

### Claim 11 (depends on 8)

The method according to claim 8,
wherein a size of the first pattern is different from a size of the second pattern.