# US 2018/0323160 A1 · Methods of forming and operating semiconductor devices including dummy chips

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- Number: US 2018/0323160 A1
- Document ID: US20180323160A1
- Status: Published application
- Kind: A1
- Application number: 16/039,652
- Filed: 2018-07-19
- Published: 2018-11-08
- Earliest claimed: 2015-06-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Shing-Yih Shih; Neng-Tai Shih
- Web page: https://patentgrep.com/patent/US20180323160A1

## CPC

- H10W 72/90: Bond pads, in general
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 74/473: {containing a filler}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

## Claims

### Claim 1

A method of forming a semiconductor device, the method comprising:
forming active bump pads within a chip mounting area;
forming electrically isolated, inactive dummy pads outside the chip mounting area and within a peripheral area, the peripheral area being adjacent to and at least partially surrounding the chip mounting area;
placing active chips on at least some of the active bump pads; and
placing dummy chips on at least some of the electrically isolated, inactive dummy pads, the dummy chips being located only on the electrically isolated, inactive dummy pads within the peripheral area.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a redistribution layer comprising a dielectric material and a metal material, wherein forming the active bump pads and the electrically isolated, inactive dummy pads comprises forming the active bump pads and the electrically isolated, inactive dummy pads over the redistribution layer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
forming a molding compound over the active chips, the dummy chips, and the redistribution layer; and
removing an upper portion of the molding compound to expose upper surfaces of the active chips and the dummy chips.

### Claim 4 (depends on 2)

The method of claim 2, wherein:
forming the active bump pads comprises electrically connecting the active bump pads to circuitry of the redistribution layer; and
forming the electrically isolated, inactive dummy pads comprises at least partially surrounding the electrically isolated, inactive dummy pads with the dielectric material of the redistribution layer.

### Claim 5 (depends on 2)

The method of claim 2, wherein placing the dummy chips comprises reducing an exposed cross-sectional area of an upper surface of the redistribution layer prior to forming the molding compound.

### Claim 6 (depends on 2)

The method of claim 2, wherein forming the redistribution layer comprises forming an interposer without forming a through substrate via (TSV) substrate.

### Claim 7 (depends on 1)

The method of claim 1, wherein placing the active chips and the dummy chips comprises placing only one active chip on a respective active bump pad and placing only one dummy chip on a respective electrically isolated, inactive dummy pad.

### Claim 8 (depends on 1)

The method of claim 1, wherein placing the active chips and the dummy chips comprises positioning the active chips and the dummy chips with upper surfaces of each of the active chips and the dummy chips being generally coplanar with one another.

### Claim 9

A method of forming a semiconductor device, the method comprising:
forming active bump pads within a chip mounting area of a redistribution layer;
connecting active chips to at least some of the active bump pads; and
providing electrically isolated dummy chips outside the chip mounting area and only within a peripheral area laterally surrounding the chip mounting area on at least two sides, the electrically isolated dummy chips being mounted directly on the redistribution layer with an adhesive.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
providing a carrier to support the redistribution layer; and
forming a passivation material between the carrier and the redistribution layer.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming a molding compound over the active chips, the electrically isolated dummy chips, and an exposed upper surface of the redistribution layer; and
thereafter removing the carrier.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
removing at least a portion of the passivation material to expose a metal material of the redistribution layer;
forming solder bumps on exposed portions of the metal material; and
thereafter separating individual packages from one another.

### Claim 13 (depends on 9)

The method of claim 9, wherein connecting the active chips comprises interconnecting at least some of the active chips to one another through the redistribution layer, at least some of the active chips comprising memory chips.

### Claim 14 (depends on 9)

The method of claim 9, wherein providing the electrically isolated dummy chips comprises providing silicon chips having sizes similar to that of the active chips.

### Claim 15

A method of operating a semiconductor device, the method comprising:
transmitting a signal between active chips and circuitry of a redistribution layer, the active chips located on active bump pads within a chip mounting area, and the active bump pads being electrically coupled to the circuitry of the redistribution layer; and
electrically isolating dummy chips from the circuitry of the redistribution layer through electrically isolated, inactive dummy pads located outside the chip mounting area and only within a peripheral area, the dummy chips located only on the electrically isolated, inactive dummy pads, and the peripheral area being adjacent to and at least partially surrounding the chip mounting area.

### Claim 16 (depends on 15)

The method of claim 15, wherein transmitting the signal between the active chips and the circuitry of the redistribution layer comprises electrically interconnecting at least some of the active chips through the redistribution layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein electrically isolating the dummy chips from the circuitry of the redistribution layer comprises physically isolating the electrically isolated, inactive dummy pads from the circuitry of the redistribution layer with a dielectric material of the redistribution layer.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
protecting the active chips, the dummy chips, and the redistribution layer with a molding compound; and
reducing warpage of the redistribution layer during operation of the semiconductor device using placement of the dummy chips within the peripheral area.

### Claim 19 (depends on 15)

The method of claim 15, further comprising transmitting the signal between the active chips and solder bumps through the redistribution layer, the solder bumps located on a side of the redistribution layer opposite the active bump pads.

### Claim 20 (depends on 19)

The method of claim 19, wherein transmitting the signal between the active chips and the solder bumps through the redistribution layer comprises transmitting the signal between the active chips and the solder bumps without using through substrate vias.