# US 2018/0323152 A1 · Semiconductor structure and fabricating method thereof

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- Number: US 2018/0323152 A1
- Document ID: US20180323152A1
- Status: Published application
- Kind: A1
- Application number: 16/022,896
- Filed: 2018-06-29
- Published: 2018-11-08
- Earliest claimed: 2015-12-17
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co. Ltd.
- Inventors: Kuo-Hung LEE; Chih-Fei LEE; Fu-Cheng CHANG; Ching-Hung KAO
- Web page: https://patentgrep.com/patent/US20180323152A1

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10D 1/68: Capacitors having no potential barriers
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/43: Layouts of interconnections
- H10W 20/496: {Capacitor integral with wiring layers}
- H10B 12/37: {the capacitor being at least partially in a trench in the substrate}
- H10D 1/042: {using deposition processes to form electrode extensions}
- H10D 1/692: {Electrodes}
- H10D 1/716: {having vertical extensions}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 50/73: {using masks for insulating materials}
- H10P 70/234: {the processing being the formation of vias or contact holes}
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10W 46/503: {Located in scribe lines}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

## Claims

### Claim 1

A semiconductor structure comprising:
a substrate comprising:
a first product region; and
an alignment region disposed adjacent the first product region;
an alignment mark feature disposed over the alignment region;
a bottom conductive layer disposed over the alignment mark feature in a substantially conformal manner;
an insulator layer disposed over the bottom conductive layer; and
a top conductive layer disposed over the insulator layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the bottom conductive layer, the insulator layer, and the top conductive layer are further disposed over the first product region to form a metal-insulator-metal (MIM) component over the first product region.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, comprising:
a dielectric layer disposed over the substrate and under the alignment mark feature.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the alignment mark feature and the bottom conductive layer are in contact with the dielectric layer.

### Claim 5 (depends on 3)

The semiconductor structure of claim 3, wherein:
the alignment mark feature protrudes from an alignment mark layer, and
the bottom conductive layer is spaced apart from the dielectric layer by the alignment mark layer.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the dielectric layer and the alignment mark layer are further disposed over the first product region.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the bottom conductive layer is in contact with a sidewall and a top surface of the alignment mark feature.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, comprising:
a first dielectric layer;
a conductive feature disposed over the first product region and extending through the first dielectric layer; and
a second dielectric layer disposed over the conductive feature, wherein the bottom conductive layer is spaced apart from the conductive feature by the second dielectric layer.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, wherein the first dielectric layer and the second dielectric layer are disposed over the first product region and the alignment region.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein:
the substrate comprises a second product region, and
the alignment region is disposed between first product region and the second product region.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein the alignment mark feature comprises silicon carbon or silicon nitride.

### Claim 12

A semiconductor structure comprising:
a conductive feature;
a dielectric layer disposed over the conductive feature;
an alignment mark feature disposed over the dielectric layer; and
a bottom conductive layer in contact with a top surface and a sidewall of the alignment mark feature.

### Claim 13 (depends on 12)

The semiconductor structure of claim 12, wherein the alignment mark feature and the bottom conductive layer are in contact with dielectric layer.

### Claim 14 (depends on 12)

The semiconductor structure of claim 12, comprising:
an insulator layer disposed over the bottom conductive layer; and
a top conductive layer disposed over the insulator layer.

### Claim 15 (depends on 12)

The semiconductor structure of claim 12, wherein:
the alignment mark feature protrudes from an alignment mark layer, and
the bottom conductive layer is spaced apart from the dielectric layer by the alignment mark layer.

### Claim 16

A semiconductor structure comprising:
a substrate comprising:
a product region; and
an alignment region disposed adjacent the product region;
an alignment mark layer disposed over the alignment region and comprising a first portion having a first height and a second portion having a second height different than the first height; and
a bottom conductive layer disposed over the first portion of the alignment mark layer and the second portion of the alignment mark layer.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, comprising:
a dielectric layer disposed under the alignment mark layer, wherein the bottom conductive layer is spaced apart from the dielectric layer by the first portion of the alignment mark layer and the second portion of the alignment mark layer.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein the first portion of the alignment mark layer is further disposed over the product region.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, wherein the alignment mark layer comprises silicon carbon or silicon nitride.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, comprising:
a first dielectric layer;
a conductive feature disposed over the product region and extending through the first dielectric layer; and
a second dielectric layer disposed over the conductive feature, wherein the first portion of the alignment mark layer is spaced apart from the conductive feature by the second dielectric layer.