# US 2018/0323142 A1 · Structure Of Integrated Circuitry And A Method Of Forming A Conductive Via

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- Number: US 2018/0323142 A1
- Document ID: US20180323142A1
- Status: Published application
- Kind: A1
- Application number: 15/926,505
- Filed: 2018-03-20
- Published: 2018-11-08
- Earliest claimed: 2017-05-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Sourabh Dhir; Andrew L. Li; Sanh D. Tang; Naoyoshi Kobayashi; Katsumi Koge
- Web page: https://patentgrep.com/patent/US20180323142A1

## CPC

- H10W 20/42: Vias, e.g. via plugs
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/482: {Bit lines}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A structure of integrated circuitry, comprising:
a transistor comprising a pair of source/drain regions, a buried gate, and a channel region along the buried gate between the pair of source/drain regions;
a first conductive via electrically coupled to and projecting from one of the pair of source/drain regions, the first conductive via having a first sidewall;
a second conductive via electrically coupled to and projecting from the other of the pair of source/drain regions, the second conductive via having a second sidewall; and
an insulative layer between the first sidewall of the first conductive via and the second sidewall of the second conductive via, the insulative layer comprising:
first insulator material;
second insulator material;
third insulator material between the first and second insulator materials; and
each of the first and second insulator materials having greater k than the third insulator material.

### Claim 22 (depends on 21)

The structure of claim 21 wherein,
each of the first and second insulator materials has k greater than 4.0; and
the third insulator material has k no greater than 4.0.

### Claim 23 (depends on 21)

The structure of claim 21 further comprising a conductive line electrically coupled to and crossing above the first conductive via.

### Claim 24 (depends on 23)

The structure of claim 23 wherein the conductive line has a third sidewall, the insulative layer extending to cover the third sidewall of the conductive line.

### Claim 25 (depends on 24)

The structure of claim 24 wherein the conductive line comprises a metal and the first conductive via comprises polycrystalline semiconductor material.

### Claim 26 (depends on 21)

The structure of claim 21 wherein the insulative layer further comprises a fourth insulator material between the first and third insulator materials, each of the first and second insulator materials having greater k than the fourth insulator material.

### Claim 27 (depends on 26)

The structure of claim 26 wherein,
each of the first and second insulator materials has k greater than 4.0; and
each of the third and fourth insulator materials has K no greater than 4.0.

### Claim 28 (depends on 23)

The structure of claim 23 further comprising a capacitive element electrically coupled to the second conductive via.

### Claim 29

A structure of integrated circuitry, comprising:
a first semiconductor region having a first upper surface;
a second semiconductor region having a second upper surface that is higher than the first upper surface of the first semiconductor region;
a first conductive via electrically coupled to and projecting from the first semiconductor region, the first conductive via having a first sidewall;
a second conductive via electrically coupled to and projecting from the second semiconductor region, the second conductive via having a second sidewall; and
an isolation structure between the first and second conductive vias separating the first and second conductive vias from each other, the isolation structure comprising:
first insulator material surrounding the first conductive via; and
second insulator material intervening between the first insulator material and the second conductive via, the second insulator material comprising:
third insulator material;
fourth insulator material;
fifth insulator material between the third and fourth insulator materials; and
each of the third and fourth insulator materials having greater k than the fifth insulator material.

### Claim 30 (depends on 29)

The structure of claim 29 wherein each of the third and fourth insulator materials has greater k than the first insulator material.

### Claim 31 (depends on 30)

The structure of claim 30 wherein,
each of the third and fourth insulator materials has k greater than 4.0; and
each of the first and fifth insulator materials has k no greater than 4.0.

### Claim 32 (depends on 29)

The structure of claim 29 wherein each of the first and second conductive vias comprises a polycrystalline semiconductor material.

### Claim 33 (depends on 32)

The structure of claim 32 wherein the polycrystalline semiconductor material comprises polysilicon.

### Claim 34 (depends on 29)

The structure of claim 29 further comprising a conductive line electrically coupled to and crossing above the first conductive via.

### Claim 35 (depends on 34)

The structure of claim 34 wherein,
the first insulator material terminates substantially at the first upper surface of the first conductive via; and
the second insulator material extends to cover a sidewall of the conductive line.

### Claim 36 (depends on 35)

The structure of claim 35 wherein,
the conductive line has a third upper surface; and
the second supper surface of the second conductive via is between the first upper surface of the first conductive via and the third upper surface of the conductive line.

### Claim 37 (depends on 34)

The structure of claim 34 wherein the conductive line is different in material from each of the first and second conductive vias.

### Claim 38 (depends on 29)

The structure of claim 29 wherein,
the second insulator material further comprises sixth insulator material between the third and fifth insulator materials; and
each of the third and fourth insulator materials having greater k than each of the fifth and sixth insulator materials.

### Claim 39 (depends on 38)

The structure of claim 38 wherein,
each of the third and fourth insulator materials has K greater than 4.0; and
each of the fifth and sixth insulator materials has K no greater than 4.0.

### Claim 40 (depends on 39)

The structure of claim 39 wherein the first insulator material has k no greater than 4.0.