# US 2018/0323136 A1 · Chip package with sidewall metallization > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0323136 A1 - Document ID: US20180323136A1 - Status: Published application - Kind: A1 - Application number: 15/970,413 - Filed: 2018-05-03 - Published: 2018-11-08 - Earliest claimed: 2017-05-05 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Andre Schmenn; Damian Sojka - Web page: https://patentgrep.com/patent/US20180323136A1 ## CPC - H10W 70/657: {on sidewalls or bottom surfaces of the package substrates, interposers or redistribution layers} - H10P 54/00: Cutting or separating of wafers, substrates or parts of devices - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/019: {of bond pads} - H10W 72/073: {of die-attach connectors} - H10W 72/90: Bond pads, in general - H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/352: {comprising metals or metalloids, e.g. solders} - H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics} - H10W 72/354: {comprising polymers} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A chip package and manufacturing method is disclosed. In one example, the method includes forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating. A semiconductor wafer is bonded on a front side of the carrier wafer. An electrically conductive connection structure is formed, including at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. Material on a backside of the carrier wafer is removed to singularize the bonded wafers at the trenches into a plurality of semiconductor devices. ## Claims ### Claim 1 A manufacturing method, comprising: forming a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating; bonding a semiconductor wafer on a front side of the carrier wafer so that each of a plurality of electronic chips of the semiconductor wafer is aligned with respect to a respective one of the trenches; forming an electrically conductive connection structure at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips; and removing material on a backside of the carrier wafer to thereby singularize the bonded wafers at the trenches into a plurality of semiconductor devices. ### Claim 2 (depends on 1) The method according to claim 1, wherein the method comprises forming the carrier wafer by forming first auxiliary trenches and filling the first auxiliary trenches at least partially with electrically insulating material; forming second auxiliary trenches laterally neighboured to the first auxiliary trenches and filling the second auxiliary trenches at least partially with the electrically conductive sidewall coating; and subsequently forming the trenches between respectively two neighboured second auxiliary trenches so that two opposing sidewalls of the respective trench are at least partially covered with the electrically conductive sidewall coating. ### Claim 3 (depends on 2) The method according to claim 2, wherein the method comprises forming the trenches extending deeper into the carrier wafer than the first auxiliary trenches and the second auxiliary trenches. ### Claim 4 (depends on 2) The method according to claim 2, wherein the first auxiliary trenches are filled with the electrically insulating material by oxidizing exposed walls of the carrier wafer followed by deposition of further electrically insulating material. ### Claim 5 (depends on 2) The method according to claim 2, wherein the second auxiliary trenches are partially filled with electrically insulating material by oxidizing exposed walls of the carrier wafer. ### Claim 6 (depends on 1) The method according to claim 1, wherein the method comprises bonding the semiconductor wafer on the front side of the carrier wafer so that the integrated circuit elements are exposed on a main surface of the semiconductor wafer opposing a bonding surface of the semiconductor wafer. ### Claim 7 (depends on 1) The method according to claim 1, wherein the method comprises forming through holes in the semiconductor wafer so that the through holes flush with the trenches. ### Claim 8 (depends on 1) The method according to claim 1, wherein the method comprises forming the electrically conductive connection structure by seed metal deposition followed by electroless plating. ### Claim 9 (depends on 1) The method according to claim 1, wherein the method comprises bonding the semiconductor wafer on the carrier wafer by adhesive material, in particular by electrically insulating adhesive material. ### Claim 10 (depends on 1) The method according to claim 1, wherein the method comprises removing the material of the carrier wafer by grinding. ### Claim 11 (depends on 1) The method according to claim 1, wherein the electrically conductive connection structure is formed to uninterruptedly electrically connect the electrically conductive sidewall coating with the integrated circuit element. ### Claim 12 An intermediate product, comprising: a carrier wafer with a plurality of trenches, each trench being at least partially covered with an electrically conductive sidewall coating; a semiconductor wafer bonded on a front side of the carrier wafer so that each of a plurality of electronic chips of the semiconductor wafer is aligned with respect to a respective one of the trenches; an electrically conductive connection structure at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of a respective one of the electronic chips. ### Claim 13 A non-encapsulated semiconductor device, comprising: a carrier body with a sidewall being at least partially covered with an electrically conductive sidewall coating; an electronic chip bonded on a base wall of the carrier body; and an electrically conductive connection structure at least partially bridging a gap between the electrically conductive sidewall coating and an integrated circuit element of the electronic chip. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, configured as a Chip-Scale-Package. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein two opposing sidewalls of the carrier body are covered at least partially with the electrically conductive sidewall coating. ### Claim 16 (depends on 13) The semiconductor device according to claim 13, comprising a circumferential electrically insulating annulus arranged between the electrically conductive sidewall coating and the carrier body. ### Claim 17 (depends on 13) The semiconductor device according to claim 13, wherein a surface of the semiconductor device has an area of not more than 0.3 mm×0.15 mm. ### Claim 18 (depends on 13) The semiconductor device according to claim 13, comprising one of the following features: the electrically conductive connection structure uninterruptedly bridges the gap between the electrically conductive sidewall coating and the integrated circuit element; and the electrically conductive connection structure bridges only part the gap between the electrically conductive sidewall coating and the integrated circuit element so that an electrically nonconductive space remains in between. ### Claim 19 (depends on 13) The semiconductor device according to claim 13, wherein the electrically conductive connection structure at least comprises a base wall section extending perpendicular to the electrically conductive sidewall coating. ### Claim 20 (depends on 13) The semiconductor device according to claim 13, wherein the electrically conductive connection structure at least comprises at least one sidewall section and at least one base wall section extending perpendicular to at least one sidewall section. ### Claim 21 (depends on 13) An electronic device, comprising: a device carrier; and a non-encapsulated semiconductor device according to claim 13 mounted on the device carrier at least partially by a portion of the electrically conductive connection structure arranged on the sidewall coating. ### Claim 22 (depends on 21) The electronic device according to claim 21, wherein the device carrier comprises one of the group consisting of a printed circuit board, and a leadframe. ### Claim 23 (depends on 21) The electronic device according to claim 21, comprising a solder structure connecting the device carrier with the electrically conductive connection structure. ### Claim 24 (depends on 21) The electronic device according to claim 21, wherein the semiconductor device is mounted on the device carrier partially by a portion of the electrically conductive connection structure being not arranged on the sidewall coating.