# US 2018/0323129 A1 · Semiconductor package having routable encapsulated conductive substrate and method

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- Number: US 2018/0323129 A1
- Document ID: US20180323129A1
- Status: Published application
- Kind: A1
- Application number: 16/032,295
- Filed: 2018-07-11
- Published: 2018-11-08
- Earliest claimed: 2015-09-08
- Assignees: Amkor Technology, Inc.
- Applicants: Amkor Technology Inc.
- Inventors: Won Bae Bang; Byong Jin Kim; Gi Jeong Kim; Jae Doo Kwon; Hyung Il Jeon
- Web page: https://patentgrep.com/patent/US20180323129A1

## CPC

- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/456: {Materials}
- H10W 70/479: {on or in insulating or insulated package substrates, interposers, or redistribution layers}
- H10W 70/6565: {recessed into the surface of the package substrates, interposers, or redistribution layers}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/047: {Attaching leadframes to insulating supports, e.g. for tape automated bonding [TAB]}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 70/442: {of multiple leadframes in a single chip}
- H10W 70/451: {Multilayered leadframes}
- H10W 70/458: {of insulating layers on leadframes}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/072: {of bump connectors}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/075: {of bond wires}
- H10W 72/354: {comprising polymers}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

## Claims

### Claim 1

A semiconductor device structure comprising:
a routable encapsulated conductive substrate comprising:
a first conductive structure encapsulated within a first laminated layer, wherein:
the first conductive structure comprises:
a first surface finish structure; and
first conductive vias connected to at least a portion of the first surface finish structure; and
the first laminated layer defines a top substrate surface of the routable encapsulated conductive substrate;
the first surface finish structure is exposed by the top substrate surface;
a second conductive structure electrically coupled to the first conductive vias and encapsulated within a second laminated layer, wherein:
the second conductive structure comprises:
a conductive pattern structure; and
conductive pads connected to the conductive pattern structure; and
the second laminated layer defines a bottom substrate surface of the routable encapsulated conductive substrate;
the second laminated layer covers a portion of the first laminated layer; and
lower surfaces of the conductive pads proximate to the bottom substrate surface are devoid of the second laminated layer so that the lower surfaces are adapted for coupling to a next level assembly;
a semiconductor device electrically coupled to the first surface finish structure; and
a package body covering the semiconductor device, at least portions of the first surface finish structure, and at least portions of the top substrate surface.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, wherein:
the first surface finish structure and the first conductive vias comprise different conductive materials.

### Claim 3 (depends on 2)

The semiconductor device structure of claim 2, wherein:
the first surface finish structure comprises silver (Ag);
the first conductive vias comprise copper (Cu).

### Claim 4 (depends on 1)

The semiconductor device structure of claim 1, wherein:
the semiconductor device is attached to the top substrate surface; and
the semiconductor device is electrically connected to the first surface finish structure with conductive wires.

### Claim 5 (depends on 1)

The semiconductor device structure of claim 1, wherein:
the semiconductor device is electrically coupled to the first surface finish structure with conductive bumps in a flip-chip configuration.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein:
a portion of the conductive pattern structure is provided devoid of conductive pads; and
the first surface finish structure has a thickness that is greater than that of the conductive pattern structure.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein:
the first surface finish structure is substantially coplanar with the top substrate surface;
surfaces of the conductive pads are recessed within openings in the second laminated layer; and
the semiconductor device further comprises conductive bumps connected to the conductive pads.

### Claim 8 (depends on 1)

The semiconductor device of claim 1 further comprising a surface finish layer connected to the conductive pads.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein:
the surface finish layer comprises one or more of nickel/gold (Ni/Au), silver (Ag) or tin (Sn).

### Claim 10

A semiconductor device structure comprising:
a routable encapsulated conductive substrate comprising:
a first conductive structure encapsulated within a first laminated layer, wherein:
the first conductive structure comprises:
a first surface finish structure; and
first conductive vias connected to at least a portion of the first surface finish structure; and
the first laminated layer defines a top substrate surface of the routable encapsulated conductive substrate;
the first surface finish structure is exposed by the top substrate surface;
a second conductive structure electrically coupled to the first conductive vias and encapsulated within a second laminated layer, wherein:
the second conductive structure comprises:
a conductive pattern structure; and
conductive pads connected to the conductive pattern structure; and
the second laminated layer defines a bottom substrate surface of the routable encapsulated conductive substrate;
the second laminated layer covers a portion of the first laminated layer; and
lower surfaces of the conductive pads proximate to the bottom substrate surface are devoid of the second laminated layer so that the lower surfaces are adapted for coupling to a next level assembly;
a semiconductor device electrically coupled to the first surface finish structure; and
a package body covering the semiconductor device, at least portions of the first surface finish structure, and at least portions of the top substrate surface, wherein:
the first surface finish structure and the first conductive vias comprise different conductive materials.

### Claim 11 (depends on 10)

The semiconductor device structure of claim 10, wherein:
the first surface finish structure comprises silver (Ag); and
the first conductive vias comprise copper (Cu).

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein:
the first surface finish structure is substantially coplanar with the top substrate surface;
surfaces of the conductive pads are recessed within openings in the second laminated layer; and
the semiconductor device further comprises conductive bumps connected to the conductive pads.

### Claim 13 (depends on 10)

The semiconductor device of claim 10 further comprising a surface finish layer connected to the conductive pads.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein:
the surface finish layer comprises one or more of nickel/gold (Ni/Au), silver (Ag) or tin (Sn).

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein:
the semiconductor device is electrically coupled to the first surface finish structure with conductive bumps in a flip-chip configuration.

### Claim 16

A method of manufacturing a semiconductor device having a routable encapsulated conductive substrate comprising:
providing a routable encapsulated conductive substrate comprising:
a first conductive structure encapsulated within a first laminated layer, wherein:
the first conductive structure comprises:
a first surface finish structure; and
first conductive vias connected to at least a portion of the first surface finish structure; and
the first laminated layer defines a top substrate surface of the routable encapsulated conductive substrate;
the first surface finish structure is exposed by the top substrate surface;
a second conductive structure electrically coupled to the first conductive vias and encapsulated within a second laminated layer, wherein:
the second conductive structure comprises:
a conductive pattern structure; and
conductive pads connected to the conductive pattern structure; and
the second laminated layer defines a bottom substrate surface of the routable encapsulated conductive substrate;
the second laminated layer covers a portion of the first laminated layer; and
lower surfaces of the conductive pads proximate to the bottom substrate surface are devoid of the second laminated layer so that the lower surfaces are adapted for coupling to a next level assembly;
electrically coupling a semiconductor device to the first surface finish structure; and
providing a package body covering the semiconductor device, at least portions of the first surface finish structure, and at least portions of the top substrate surface, wherein:
the first surface finish structure and the first conductive vias comprise different conductive materials.

### Claim 17 (depends on 16)

The method of claim 16, wherein providing the routable encapsulated conductive substrate comprises:
providing the first surface finish structure on a carrier;
providing the conductive vias on at least portions of the first surface finish structure;
providing the first laminated layer covering the carrier, the first surface finish structure, and the conductive vias;
providing the conductive pattern structure connected to the conductive vias;
providing the conductive pads connected to at least a portion of the conductive pattern structure;
providing the second laminated layer covering the first laminated layer, the conductive pattern structure and the conductive pads; and
removing the carrier.

### Claim 18 (depends on 16)

The method of claim 16, wherein:
providing the routable encapsulated conductive substrate comprises:
providing the first surface finish structure substantially coplanar with the top substrate surface; and
providing surfaces of the conductive pads are recessed within openings in the second laminated layer; and
the method further comprises providing one or more of a conductive bumps connected to the conductive pads or a finishing layer connected to the conductive pads.

### Claim 19 (depends on 16)

The method of claim 16, wherein:
electrically coupling the semiconductor device comprises electrically coupling the semiconductor device to the first surface finish structure with conductive bumps in a flip-chip configuration.

### Claim 20 (depends on 16)

The method of claim 16, wherein:
providing the routable encapsulated conductive substrate comprises:
providing the first surface finish structure comprising silver (Ag); and
providing the first conductive vias comprising copper (Cu).