# US 2018/0323121 A1 · Multi-Layer Substrate For Semiconductor Packaging

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- Number: US 2018/0323121 A1
- Document ID: US20180323121A1
- Status: Published application
- Kind: A1
- Application number: 16/032,085
- Filed: 2018-07-11
- Published: 2018-11-08
- Earliest claimed: 2012-03-26
- Assignees: Advanpack Solutions Pte Ltd.
- Applicants: Advanpack Solutions Pte Ltd
- Inventors: Shoa Siong LIM; Hwee Seng CHEW
- Web page: https://patentgrep.com/patent/US20180323121A1

## CPC

- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/048: {Mechanical treatments, e.g. punching, cutting, deforming or cold welding}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/01: Manufacture or treatment
- H10W 74/473: {containing a filler}
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/0198: {batch processes}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- Y10T 29/49121: Beam lead frame or beam lead device
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

The present invention provides a semiconductor substrate (105, 105a) comprising two or more layers of built-up structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer, comprising a conductor trace layer (114a,) and an interconnect (118a, 218a), is molded in a resin molding compound. A top surface of the molded compound is abrasively ground and then deposited with an adhesion layer (123, 124, 224). A multi-layer substrate (105, 105a) is then obtained after an outermost conductor trace layer (128a, 228a) is formed on the adhesion layer and the carrier (110) or reinforcing ring (110b) is removed.

## Claims

### Claim 1

A multi-layer semiconductor substrate comprising:
a sacrificial carrier that is electrically conductive and chemically etchable;
a first conductor trace layer formed on the sacrificial carrier;
a second conductor trace layer; and
a (first) interconnect layer disposed between the first and second conductor trace layers, wherein studs connect selected areas between the first and second conductor trace layers.

### Claim 2 (depends on 1)

A multi-layer semiconductor substrate according to claim 1, wherein the first conductor trace layer and (first) interconnect stud layer are encapsulated in a resin molding compound.

### Claim 3 (depends on 2)

A multi-layer semiconductor substrate according to claim 2, wherein the resin molding is abrasively ground to expose the (first) interconnect studs and the ground surface is then deposited a conductor seed layer.

### Claim 4 (depends on 3)

A multi-layer semiconductor substrate according to claim 3, wherein the conductor seed layer is built on an adhesion layer to promote adhesion of the second conductor trace layer.

### Claim 5 (depends on 4)

A multi-layer semiconductor substrate according to claim 4, wherein the adhesion layer comprises a polyimide or a woven glass fiber laminate.

### Claim 6 (depends on 3)

A multi-layer semiconductor substrate according to claim 3, further comprising a second insulating layer deposited on the second conductor trace layer, so that the second insulating layer is selectively removed to expose areas of the second conductor trace layer for external electrical connections.

### Claim 7 (depends on 3)

A multi-layer semiconductor substrate according to claim 3, further comprising one or more intermediate built-up layers, with each intermediate built-up layer comprising a conductor trace component layer and an interconnect stud component layer, and each built-up layer is encapsulated in a resin molding compound so that the molding surface is abrasively ground and then deposited with a conductor seed layer.

### Claim 8 (depends on 7)

A multi-layer semiconductor substrate according to claim 7, wherein an internal portion of the sacrificial carrier is etched away so that a reinforcement carrier ring remains on a peripheral area of the substrate or around a gang of conductor layouts.