# US 2018/0323114 A1 · Bulk CMOS RF Switch With Reduced Parasitic Capacitance

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- Number: US 2018/0323114 A1
- Document ID: US20180323114A1
- Status: Published application
- Kind: A1
- Application number: 15/587,969
- Filed: 2017-05-05
- Published: 2018-11-08
- Earliest claimed: 2017-05-05
- Assignees: Newport Fab, LLC dba Jazz Semiconductor
- Applicants: Newport Fab, LLC dba Jazz Semiconductor, Inc.
- Inventors: Edward J. Preisler; Marco Racanelli; Paul D. Hurwitz
- Web page: https://patentgrep.com/patent/US20180323114A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/114: {PN junction isolations}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10P 30/22: using masks
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/50: Isolation regions based on field-effect
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Bulk CMOS RF switches having reduced parasitic capacitance are achieved by reducing the size and/or doping concentration of the switch's N-doped tap (N-Tap) element, which is used to conduct a bias voltage to a Deep N-Well disposed under each switch's P-Type body implant (P-Well). Both the P-Well and the N-Tap extend between an upper epitaxial silicon surface and an upper boundary of the Deep N-well. A low-doping-concentration approach utilizes intrinsic (lightly doped) N-type epitaxial material to provide a body region of the N-Tap element, whereby an N+ surface contact diffusion is separated from an underlying section of the Deep N-well by a region of intrinsic epitaxial silicon. An alternative reduced-size approach utilizes an open-ring deep trench isolation structure that surrounds the active switch region (e.g., the Deep N-well and P-Well), and includes a relatively small-sized N-Tap region formed in an open corner region of the isolation structure.

## Claims

### Claim at position 1

1-5. (canceled)

### Claim 6

A method for fabricating a bulk CMOS RF switch in an active switch area of a base structure, the method comprising:
forming an epitaxial silicon layer over a semiconductor substrate such that a Deep N-well is at least partially formed in a first epitaxial region of said epitaxial layer adjacent to an interface between the epitaxial silicon layer and said substrate, said epitaxial silicon layer having a resistivity in the range of 0.5 to 2 ohm-cm, and said Deep N-well having a second nominal N-type doping concentration in the range of 1×1016 to 1×1018 atoms per cubic centimeter;
forming a P-well by implanting a first P-type dopant into a second epitaxial region of the epitaxial silicon layer, the second epitaxial region being located above a first epitaxial layer portion of the first epitaxial region and the first P-type dopant being implanted through an upper epitaxial surface of the epitaxial silicon layer such that the P-well extends from the upper epitaxial surface to a first upper boundary region of the first epitaxial layer portion;
disposing a mask over the entire active switch area during a first N-type implant such that a third epitaxial region of the epitaxial silicon layer, which is located above a second epitaxial layer portion of the first epitaxial region, maintains said first nominal N-type doping concentration;
performing a second N-type implant during which spaced-apart first and second contact diffusions are formed in the P-Well, and a third contact diffusion is formed in the third epitaxial region, said third contact diffusion being formed such that said third contact diffusion is separated from a second upper boundary region of the second epitaxial layer portion by a body region comprising said intrinsic epitaxial material; and
forming backend metallization structures over including metal via structures connected to the first, second and third contact diffusions while the body region comprises said intrinsic epitaxial material.

### Claim 7 (depends on 6)

The method of claim 6, further comprising, prior to forming said P-Well, forming peripheral field isolation sections around said switch area and an intermediate field isolation section between the second and third epitaxial regions.

### Claim 8 (depends on 7)

The method of claim 7, wherein forming said peripheral field isolation sections and said intermediate field isolation section comprises forming shallow-trench isolation structures.

### Claim 9 (depends on 6)

The method of claim 6, further comprising, prior to performing said second N-type implant, forming a gate structure over said P-Well.

### Claim at position 6

10-13. (canceled)

### Claim 14

A method for fabricating a bulk CMOS RF switch in an active switch area of a base structure, the method comprising:
forming an epitaxial silicon layer over a semiconductor substrate such that a Deep N-well is at least partially formed in a first epitaxial region of said epitaxial layer adjacent to an interface between the epitaxial silicon layer and said substrate, said epitaxial silicon layer having a first nominal N-type doping concentration that produces a resistivity in the range of 0.5 to 2 ohm-cm, and said Deep N-well having a second nominal N-type doping concentration in the range of 1×1016 to 1×1018 atoms per cubic centimeter;
forming a P-well by implanting a first P-type dopant into a second epitaxial region of the epitaxial silicon layer, the second epitaxial region being located above a first epitaxial layer portion of the first epitaxial region and the first P-type dopant being implanted through an upper epitaxial surface of the epitaxial silicon layer such that the P-well extends from the upper epitaxial surface to a first upper boundary region of the first epitaxial layer portion;
disposing a mask over the entire active switch area during a first N-type implant such that a third epitaxial region of the epitaxial silicon layer, which is located above a second epitaxial layer portion of the first epitaxial region, maintains said first nominal N-type doping concentration;
performing a second N-type implant during which spaced-apart first and second contact diffusions are formed in the P-Well, and a third contact diffusion is formed in the third epitaxial region, said third contact diffusion being formed such that said third contact diffusion is separated from a second upper boundary region of the second epitaxial layer portion by a body region comprising said intrinsic epitaxial material; and
forming backend metallization structures over including metal via structures connected to the first, second and third contact diffusions while the body region comprises said intrinsic epitaxial material.

### Claim 15 (depends on 14)

The method of claim 14, further comprising, prior to forming said P-Well, forming peripheral field isolation sections around said switch area and an intermediate field isolation section between the second and third epitaxial regions.

### Claim 16 (depends on 15)

The method of claim 15, wherein forming said peripheral field isolation sections and said intermediate field isolation section comprises forming shallow-trench isolation structures.

### Claim 17 (depends on 14)

The method of claim 14, further comprising, prior to performing said second N-type implant, forming a gate structure over said P-Well.