# US 2018/0323113 A1 · Integration scheme for gate height control and void free rmg fill

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0323113 A1
- Document ID: US20180323113A1
- Status: Published application
- Kind: A1
- Application number: 16/038,977
- Filed: 2018-07-18
- Published: 2018-11-08
- Earliest claimed: 2017-04-21
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Suraj Kumar PATIL; Katsunori ONISHI; Pei LIU; Chih-Chiang CHANG
- Web page: https://patentgrep.com/patent/US20180323113A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.

## Claims

### Claim 1

A device comprising:
an interlayer dielectric (ILD) over a silicon (Si) fin;
first and second cavities in the ILD, each over and perpendicular to the Si fin;
a high-K dielectric layer on side and bottom surfaces of the first and second cavities;
a p-type work function (pWF) metal layer over the high-K dielectric layer in the first and second cavities;
an n-type work function (nWF) metal layer over the pWF metal layer and over edges of the pWF metal layer in the first cavity and over the high-K dielectric layer in the second cavity;
a barrier metal layer over the nWF metal layer and over edges of the nWF layer,
wherein the first and second cavities comprise a low-resistive metal filling with a bump at a center of each cavity.

### Claim 2 (depends on 1)

The device according to claim 1, wherein the high-K dielectric layer has a thickness of 5 angstrom (Å) to 25 Å.

### Claim 3 (depends on 1)

The device according to claim 1, wherein the low-resistive metal bump extends to a height of 14 nm to 40 nm above the Si fin.

### Claim 4 (depends on 1)

The device according to claim 1, wherein the pWF metal layer has a thickness of 5 Å to 50 Å.

### Claim 5 (depends on 1)

The device according to claim 1, wherein the barrier metal layer has a thickness of 25 Å to 75 Å.

### Claim 6 (depends on 1)

The device according to claim 1, wherein the first low-resistive metal filled cavity forms a long channel device.

### Claim 7 (depends on 6)

The device according to claim 6, wherein the second low-resistive metal filled forms a short channel device.

### Claim 8 (depends on 7)

The device according to claim 7, wherein a width of the long channel device is 2 to 12 times a width of the short channel device.

### Claim 9

A device comprising:
a dielectric layer over a silicon (Si) fin;
first and second cavities in the dielectric, each over and perpendicular to the Si fin;
a high-K dielectric layer on side and bottom surfaces of the first and second cavities;
a p-type work function (pWF) layer over the high-K dielectric layer in the first and second cavities;
an n-type work function (nWF) layer over the pWF layer and over edges of the pWF layer in the first cavity and over the high-K dielectric layer in the second cavity; and
a barrier layer over the nWF layer and over edges of the nWF layer,
wherein the first and second cavities comprise a metal filling with a bump at a center of each cavity.

### Claim 10 (depends on 9)

The device according to claim 9, wherein the high-K dielectric layer has a thickness of 5 angstrom (Å) to 25 Å.

### Claim 11 (depends on 9)

The device according to claim 9, wherein the bump comprises a low-resistive metal and extends to a height of 14 nm to 40 nm above the Si fin.

### Claim 12 (depends on 9)

The device according to claim 9, wherein the pWF layer comprises a metal having a thickness of 5 Å to 50 Å.

### Claim 13 (depends on 9)

The device according to claim 9, wherein the barrier layer comprises a metal having a thickness of 25 Å to 75 Å.

### Claim 14

A method comprising:
forming an interlayer dielectric (ILD) over a silicon (Si) fin;
forming first and second cavities in the ILD over and perpendicular to the Si fin, the first cavity having a greater width than the second cavity;
forming a high-K dielectric layer to a thickness of 5 angstrom (Å) to 25 Å over the ILD and in the first and second cavities;
forming a p-type work function (pWF) metal layer by atomic layer deposition (ALD) to a thickness of 5 Å to 50 Å in the first and second cavities;
recessing the pWF metal layer by chamfering to a first height of 2 nanometers (nm) to 25 nm above the Si fin;
forming an n-type work function (nWF) metal layer by ALD in the cavities over the exposed high-K dielectric layer and the pWF metal layer;
recessing the nWF metal layer by chamfering to a second height of 4 nm to 30 nm above the Si fin, but covering an edge of the pWF metal layer;
forming a barrier metal layer by metal organic chemical vapor deposition (MOCVD), ALD, physical vapor deposition (PVD) to a thickness of 25 Å to 75 Å over the high-K dielectric layer and the nWF metal layer;
filling the first and second cavities with low-resistive metal;
removing portions of the low resistive metal fill by chemical mechanical planarization (CMP); and
performing reactive ion etching (RIE), recessing the barrier metal layer, the high-K dielectric layer, and the low-resistive metal to a third height 9 nm to 35 nm above the Si fin except for a low-resistive metal to bump or a final gate height extending to 14 nm to 40 nm above the Si fin at a center of each cavity.

### Claim 15 (depends on 14)

The method according to claim 14, comprising:
chamfering the pWF and nWF metal layers by maskless process comprising spin-on hard-mask or optical-planarization layer (SOH/OPL) coatings, RIE, and work function material (WFM) wet etch removal.

### Claim 16 (depends on 14)

The method according to claim 14, wherein the first cavity forms a long channel device

### Claim 17 (depends on 16)

The method according to claim 16, wherein the second cavity forms a short channel device.

### Claim 18 (depends on 17)

The method according to claim 17, further comprising controlling a height of the final gate height in the first and second cavities.

### Claim 19 (depends on 18)

The method according to claim 18, comprising forming a width of the long channel device to 2 to 12 times the width of the short channel device.

### Claim 20 (depends on 17)

The method according to claim 17, comprising chamfering the long channel device and the short channel device simultaneously.