# US 2018/0323112 A1 · Structure and formation method of fin-like field effect transistor

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- Number: US 2018/0323112 A1
- Document ID: US20180323112A1
- Status: Published application
- Kind: A1
- Application number: 16/025,786
- Filed: 2018-07-02
- Published: 2018-11-08
- Earliest claimed: 2014-06-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shiu-Ko JANGJIAN; Tzu Kai LIN; Chi-Cherng JENG
- Web page: https://patentgrep.com/patent/US20180323112A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a fin structure over the semiconductor substrate. The semiconductor device also includes a gate stack covering a portion of the fin structure and an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack. The semiconductor device further includes a semiconductor protection layer over the epitaxially grown source/drain structure. The semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure.

## Claims

### Claim 1

A semiconductor device structure, comprising:
a fin structure extending over a semiconductor substrate;
a gate stack covering a portion of the fin structure;
an epitaxially grown source/drain structure over the fin structure and adjacent to the gate stack;
a semiconductor protection layer over the epitaxially grown source/drain structure, wherein the semiconductor protection layer has an atomic concentration of silicon greater than that of the epitaxially grown source/drain structure;
a dielectric layer over the semiconductor substrate; and
a contact hole extending through the dielectric layer to a first portion of the semiconductor protection layer, wherein the semiconductor protection layer has a first thickness at the first portion and a second thickness under the dielectric layer, wherein the second thickness is greater than the first thickness.

### Claim 2 (depends on 1)

The semiconductor device structure of claim 1, wherein the semiconductor protection layer is not between the gate stack and the portion of the fin structure covered by the gate stack.

### Claim 3 (depends on 1)

The semiconductor device structure of claim 1, wherein the semiconductor protection layer is in direct contact with the epitaxially grown source/drain structure.

### Claim 4 (depends on 1)

The semiconductor device structure of claim 1, wherein the semiconductor protection layer is made of a substantially pure silicon material.

### Claim 5 (depends on 1)

The semiconductor device structure of claim 1, wherein the atomic concentration of silicon of the semiconductor protection layer is in a range from about 50% to about 99%.

### Claim 6 (depends on 1)

The semiconductor device structure of claim 1, wherein the atomic concentration of silicon of the semiconductor protection layer gradually decreases along a direction from a surface of the semiconductor protection layer towards the epitaxially grown source/drain structure.

### Claim 7 (depends on 1)

The semiconductor device structure of claim 1, wherein the first thickness is between approximately 2 nm and about 10 nm.

### Claim 8 (depends on 1)

The semiconductor device structure of claim 1, wherein the semiconductor protection layer is disposed on a first portion of a surface of the epitaxially grown source/drain structure and a support element is disposed on a second portion of the surface of the epitaxially grown source/drain structure.

### Claim 9 (depends on 8)

The semiconductor device structure of claim 8, wherein the support element is at least one of silicon nitride, silicon oxynitride, or silicon carbide.

### Claim 10 (depends on 8)

The semiconductor device structure of claim 8, wherein the support element interfaces the semiconductor protection layer.

### Claim 11

A semiconductor device structure, comprising:
a first fin structure extending from a semiconductor substrate;
a gate stack covering a portion of the first fin structure;
a first epitaxially grown source/drain structure over the first fin structure;
a second fin structure over the semiconductor substrate;
a second epitaxially grown source/drain structure over the second fin structure;
a first semiconductor protection layer the first epitaxially grown source/drain structure, wherein the first semiconductor protection layer has an atomic concentration of silicon greater than that of the first epitaxially grown source/drain structure, wherein the first semiconductor protection layer has a first terminal edge adjacent a support element and a second terminal edge adjacent a spacer element disposed on a sidewall of the gate stack; and
a second semiconductor protection layer over the second epitaxially grown source/drain structure, wherein the second semiconductor protection layer has an atomic concentration of silicon greater than that of the second epitaxially grown source/drain structure.

### Claim 12 (depends on 11)

The semiconductor device structure of claim 11, wherein the second semiconductor protection layer has a first terminal edge abutting an isolation feature extending between the first and second fin structures and a second terminal edge abutting spacer elements of a second gate stack over the second fin structure.

### Claim 13 (depends on 11)

The semiconductor device structure of claim 11, wherein the first semiconductor protection layer has a first thickness at a first region and a second thickness at a second region, the first thickness less than the second thickness.

### Claim 14 (depends on 13)

The semiconductor device structure of claim 13, wherein the first region is within a contact hole.

### Claim 15 (depends on 11)

The semiconductor device structure of claim 11, wherein at least one of the first semiconductor protection layer and the second semiconductor protection layer is made of a substantially pure silicon material.

### Claim 16 (depends on 11)

The semiconductor device structure of claim 11, wherein the atomic concentration of silicon of the first semiconductor protection layer or the second semiconductor protection layer is in a range from about 50% to about 99%.

### Claim 17 (depends on 16)

The semiconductor device structure of claim 16, wherein the atomic concentration of silicon of the first semiconductor protection layer gradually decreases along a direction from a surface of the first semiconductor protection layer towards the first epitaxially grown source/drain structure.

### Claim 18

A method of fabricating a semiconductor device structure, comprising:
forming a first fin structure and a second fin structure over a semiconductor substrate;
forming a first gate stack over a portion of the first fin structure and a second gate stack over a portion of the second fin structure;
forming a first source/drain structure adjacent the first gate stack while masking a portion of the second fin structure;
after forming the first source/drain structure, forming a first protection layer over the first source/drain structure;
forming a second source/drain structure adjacent the second gate stack while masking the first source/drain structure;
depositing a dielectric layer over the first source/drain structure and the second source/drain structure; and
patterning the dielectric layer to form a contact hole over the first source/drain structure, wherein an exposed portion of the first protection layer within the contact hole is thinned.

### Claim 19 (depends on 18)

The method of claim 18, further comprising: wherein the first gate stack is disposed on the first fin structure during the forming the first protection layer.

### Claim 20 (depends on 18)

The method of claim 18, wherein an atomic concentration of silicon is varied during the depositing of the first protection layer.