# US 2018/0323110 A1 · Hdp fill with reduced void formation and spacer damage

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- Number: US 2018/0323110 A1
- Document ID: US20180323110A1
- Status: Published application
- Kind: A1
- Application number: 16/038,426
- Filed: 2018-07-18
- Published: 2018-11-08
- Earliest claimed: 2015-06-25
- Assignees: International Business Machines Corporation; Globalfoundries Inc.
- Applicants: International Business Machines Corporation; Globalfoundries Inc.
- Inventors: Huiming Bu; Andrew M. Greene; Balasubramanian Pranatharthiharan; Ruilong Xie
- Web page: https://patentgrep.com/patent/US20180323110A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10D 84/0133: {Manufacturing common source or drain regions between multiple IGFETs}
- H10D 84/0158: {the components including FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of high aspect ratio gate structures formed adjacent to one another and forming gaps therebetween, the high aspect ratio gate structures including a top surface;
spacers formed on sidewalls of the high aspect ratio structures, the spacers having a higher etch resistance than underlying materials to maintain dimensions of the spacers during etch processes;
the gaps being filled with:
a protection layer formed on the spacers to a height on the spacers;
a flowable dielectric formed to below the height within the protection layer; and
a high density plasma dielectric fill above the height.

### Claim 2 (depends on 1)

The device as recited in claim 1, wherein the spacers include SiBCN.

### Claim 3 (depends on 1)

The device as recited in claim 1, wherein the spacers includes a thickness of 12 nm or less to increase a gap size between each of the high aspect ratio gate structures without altering a pitch between each of the high aspect ratio gate structures.

### Claim 4 (depends on 3)

The device as recited in claim 3, wherein the gap size between the high aspect ratio structures is free of voids.

### Claim 5 (depends on 1)

The device as recited in claim 1, wherein the protection layer includes a nitride.

### Claim 6 (depends on 1)

The device as recited in claim 1, wherein the plurality of high aspect ratio structures includes a high to width ratio greater than 1:1.

### Claim 7 (depends on 1)

The device as recited in claim 1, wherein the plurality of high aspect ratio structures includes a high to width ratio greater than 3:1.

### Claim 8 (depends on 1)

The device as recited in claim 1, wherein each of the plurality of high aspect ratio structures includes at least a gate material and a first dielectric layer.

### Claim 9 (depends on 8)

The device as recited in claim 8, wherein the first dielectric layer includes a material having a higher etch resistance than SiN.

### Claim 10 (depends on 8)

The device as recited in claim 8, wherein the first dielectric layer includes SiBCN.

### Claim 11 (depends on 8)

The device as recited in claim 8, wherein the spacers exceed a height of the gate material and the first dielectric layer such that the spacers form horns on top corners of the spacers.

### Claim 12 (depends on 1)

The device as recited in claim 1, wherein the spacers exceed a height of the top surface of the high aspect ratio gate structures such that the spacers form horns on top corners of the spacers.

### Claim 13 (depends on 1)

The device as recited in claim 1, further comprising a contact liner and a metal contact.

### Claim 14 (depends on 1)

The device as recited in claim 1, wherein the source and drain regions are disposed on opposite sides of each of the plurality of high aspect ratio gate structures and adjacent to the spacers.

### Claim 15

A method for filling gaps between structures in a semiconductor device, comprising:
forming a spacer dielectric layer over a plurality of high aspect ratio structures, the plurality of high aspect ratio structures adjacent to one another to provide gaps therebetween;
removing the spacer dielectric layer from horizontal surfaces to form spacers on sidewalls of the high aspect ratio structures;
forming source and drain regions adjacent to the spacers;
conformally depositing a protection layer over the high aspect ratio structures and the source and drain regions;
filling the gaps with a flowable dielectric;
recessing the flowable dielectric to a height along the sidewalls of the high aspect ratio structures such that the protection layer protects the spacers of the high aspect ratio structures; and
selectively removing the protection layer above the height to maintain a thickness of the spacers.

### Claim 16 (depends on 15)

The method as recited in claim 15, wherein forming the plurality of high aspect ratio structures includes patterning a stack of layers including at least a gate material and a first dielectric layer.

### Claim 17 (depends on 15)

The method as recited in claim 15, wherein forming the spacer dielectric layer over the high aspect ratio structures includes conformally depositing the spacer dielectric layer with a thickness of 12 nm or less to increase a gap size between high aspect ratio structures without altering a pitch between the high aspect ratio structures.

### Claim 18 (depends on 17)

The method as recited in claim 17, further comprising filling the gaps by a high density plasma fill, wherein filling the gaps by the high density plasma fill includes avoiding formation of voids by providing the gap size that has been increased.

### Claim 19 (depends on 15)

The method as recited in claim 15, wherein selectively removing the protection layer includes forming horns on top corners of each of the plurality of high aspect ratio structures.

### Claim 20 (depends on 15)

The method as recited in claim 15, further comprising forming contact holes by etching through the flowable dielectric and the protection layer.