# US 2018/0323097 A1 · Expansion method, method for manufacturing semiconductor device, and semiconductor device

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- Number: US 2018/0323097 A1
- Document ID: US20180323097A1
- Status: Published application
- Kind: A1
- Application number: 15/983,158
- Filed: 2018-05-18
- Published: 2018-11-08
- Earliest claimed: 2012-12-26
- Assignees: Hitachi Chemical Company, Ltd.
- Applicants: Hitachi Chemical Company, Ltd.
- Inventors: Yukihiro IWANAGA; Kouji SUZUMURA; Tatsuya SAKUTA
- Web page: https://patentgrep.com/patent/US20180323097A1

## CPC

- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/50: for positioning, orientation or alignment
- H10P 72/7404: {the wafer tape being a laminate of three or more layers, e.g. including additional layers beyond a base layer and an uppermost adhesive layer}
- H10W 72/013: {of die-attach connectors}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/742: {involving stretching of the auxiliary support post dicing}
- H10P 72/7438: {with parts of the auxiliary support remaining in the finished device}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/354: {comprising polymers}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment of the present invention relates to an expansion method comprising: a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape, a step (IIA) of expanding the dicing tape with the laminate in a cooled state, a step (IIB) of loosening the expanded dicing tape, and a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening the spaces between the chips.

## Claims

### Claim 1

An expansion method comprising:
a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape,
a step (IIA) of expanding the dicing tape with the laminate in a cooled state,
a step (IIB) of loosening the expanded dicing tape, and
a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.

### Claim 2 (depends on 1)

An expansion method according to claim 1 comprising:
a step (Ia) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film, a dicing tape and a frame,
a step (Ib) of supplying the laminate to a height-adjustable expansion stage of an expansion apparatus comprising the expansion stage and a fastening member capable of fastening the frame,
a step (Ic) of fastening the frame using the fastening member, a step (IIa) of raising the expansion stage and expanding the dicing tape with the laminate in a cooled state,
a step (IIb) of lowering the raised expansion stage and loosening the expanded dicing tape, and
a step (IIc) of raising the expansion stage and expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.

### Claim 3 (depends on 1)

An expansion method according to claim 1 comprising:
a step (Ia′) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film, a dicing tape and a frame,
a step (Ib′) of supplying the laminate to a height-adjustable expansion ring of an expansion apparatus comprising the expansion ring and a fastening member capable of fastening the frame,
a step (Ic′) of fastening the frame using the fastening member, a step (IIa′) of raising the expansion ring and expanding the dicing tape with the laminate in a cooled state,
a step (IIb′) of lowering the raised expansion ring and loosening the expanded dicing tape, and
a step (IIc′) of raising the expansion ring and expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.

### Claim 4 (depends on 1)

The expansion method according to claim 1, wherein expansion of the dicing tape is performed by applying an external force to the dicing tape, and an external force applied to the dicing tape in the step (IIC) is greater than an external force applied to the dicing tape in the step (IIA).

### Claim 5 (depends on 1)

A method for manufacturing a semiconductor device comprising:
a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape,
a step (II) of expanding the dicing tape, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips,
a step (III) of picking up a chip from the dicing tape,
and a step (IV) of die bonding the chip to an adherend, wherein
the step (I) and the step (II) are performed using the expansion method according to claim 1.

### Claim 6 (depends on 5)

A semiconductor device having an adherend, and a chip bonded to the adherend, wherein the semiconductor device is manufactured using the method for manufacturing a semiconductor device according to claim 5.

### Claim 7

An expansion method comprising:
a step (I) of preparing a laminate having a semiconductor wafer in which modified sections have been formed along intended cutting lines, a die bonding film and a dicing tape,
a step (IIA) of expanding the dicing tape with the laminate in a cooled state,
a step (IIB) of loosening the expanded dicing tape for not more than 10 seconds, and
a step (IIC) of expanding the dicing tape with the laminate in a cooled state, dividing the semiconductor wafer and the die bonding film into chips along the intended cutting lines, and widening spaces between the chips.