# US 2018/0323073 A1 · Fabrication of fins using variable spacers

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- Number: US 2018/0323073 A1
- Document ID: US20180323073A1
- Status: Published application
- Kind: A1
- Application number: 16/040,093
- Filed: 2018-07-19
- Published: 2018-11-08
- Earliest claimed: 2016-03-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: KANGGUO CHENG
- Web page: https://patentgrep.com/patent/US20180323073A1

## CPC

- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 48/30: Devices controlled by electric currents or voltages
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 30/22: using masks
- H10P 50/242: {of Group IV materials}
- H10P 50/287: {by chemical means}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 10/12: {comprising a MOSFET load element}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.

## Claims

### Claim 1

A method of fabricating semiconductor fins, comprising:
patterning a film stack to produce one or more sacrificial mandrels having sidewalls;
exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation;
oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars;
removing the one or more sacrificial mandrels; and
forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern.

### Claim 2 (depends on 1)

The method of claim 1, wherein the one or more sacrificial mandrels are amorphous silicon.

### Claim 3 (depends on 1)

The method of claim 1, wherein the ion beam impinges the sidewall on one side of the one or more sacrificial mandrels at an angle that shadows the opposite sidewall of the one or more sacrificial mandrels.

### Claim 4 (depends on 1)

The method of claim 1, wherein the oxide pillars formed from opposite sidewalls of the one or more sacrificial mandrels have different widths.

### Claim 5 (depends on 4)

The method of claim 4, which further comprises removing the plurality of oxide pillars; and
transferring the spacer pattern to the substrate to produce a plurality of fins, wherein the plurality of fins have a predefined pitch.

### Claim 6 (depends on 5)

The method of claim 5, which further comprises forming trenches having varying depths between the plurality of fins.

### Claim 7 (depends on 1)

The method of claim 1, wherein the spacers are formed by conformal deposition on at least opposite sides of each of the plurality of oxide pillars.

### Claim 8 (depends on 7)

The method of claim 7, wherein the spacers are amorphous carbon.

### Claim 9 (depends on 1)

The method of claim 1, wherein the sidewall on one side of the one or more sacrificial mandrels is exposed to an ion beam comprising a p-type dopant.

### Claim 10 (depends on 9)

The method of claim 9, wherein the p-type dopant is boron and the sacrificial mandrels are amorphous silicon.

### Claim 11

A method of fabricating semiconductor fins, comprising:
forming a film stack on a substrate, where the film stack includes
a nitride layer on the substrate,
an oxide layer on the nitride layer,
a sacrificial mandrel layer on the oxide layer,
and a capping layer on the sacrificial mandrel layer;
patterning the capping layer and sacrificial mandrel layer to produce one or more sacrificial mandrels having sidewalls;
exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation;
oxidizing the sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars; and
removing the one or more sacrificial mandrels.

### Claim 12 (depends on 11)

The method of claim 11, which further comprises forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, and removing the plurality of oxide pillars.

### Claim 13 (depends on 12)

The method of claim 12, wherein the sacrificial mandrels have a width in the range of about 20 nm to about 400 nm.

### Claim 14 (depends on 12)

The method of claim 12, wherein the oxide pillars on an ion-exposed sidewall of the sacrificial mandrels have a width in the range of about 15 nm to about 60 nm.

### Claim 15 (depends on 12)

The method of claim 12, wherein the spacers have a width in the range of about 5 nm to about 20 nm.

### Claim 16 (depends on 12)

The method of claim 12, further comprising etching the substrate, wherein the spacer pattern is transferred to the substrate to form a plurality of fins for forming FinFETs.

### Claim 17 (depends on 16)

The method of claim 16, wherein the spacer pattern has a predetermined pitch, P1, between two spacers and a predetermined pitch, P2, between two spacers, wherein P2≠N×P1, and N is an integer.

### Claim 18

A method of forming an intermediate fin field effect transistor (FinFET) structure, comprising:
forming a nitride layer on a semiconductor substrate;
forming an oxide layer on the nitride layer;
forming a sacrificial mandrel on the oxide layer;
exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam that chemically alters at least one exposed sidewall on one side of the sacrificial mandrel to be more susceptible to oxidation; and
forming a first oxide pillar on a first side of the sacrificial mandrel and a second oxide pillar on the opposite side of the sacrificial mandrel, wherein the first oxide pillar has a different width than the second oxide pillar.

### Claim 19 (depends on 18)

The method of claim 18, wherein the sacrificial mandrel is amorphous silicon, and the oxidation process converts at least a most heavily-implanted portion of the sacrificial mandrel to an oxide.

### Claim 20 (depends on 19)

The method of claim 19, wherein the ion beam includes an n-type dopant.