# US 2018/0323072 A1 · Method For Increasing Trench CD in EUV Patterning Without Increasing Single Line Opens or Roughness

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- Number: US 2018/0323072 A1
- Document ID: US20180323072A1
- Status: Published application
- Kind: A1
- Application number: 15/666,246
- Filed: 2017-08-01
- Published: 2018-11-08
- Earliest claimed: 2017-05-03
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: Angelique D. Raley; Jeffrey Shearer
- Web page: https://patentgrep.com/patent/US20180323072A1

## CPC

- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- H10P 50/642: {Chemical etching}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 76/2041: {Photolithographic processes}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 95/06: {Planarisation of inorganic insulating materials}
- H10P 50/283: {by chemical means}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one trim layer and at least one masking layer under the trim layer. The trim layer may have structures that have smaller linewidths than the structures of the patterned layer by utilizing an isotropic gaseous process to trim the structures of the trim layer. The structures of the trim layer, after trimming, may then be replicated in the mask layer to provide a linewidth in the mask layer that is smaller than the linewidth in the patterned layer. The technique may allow nanometer control of an EUV lithography process at pitches of 36 nm or less. In one embodiment, the technique may be utilized to provide an EUV lithography process for increasing the trench dimensions in a BEOL trench formation process step.

## Claims

### Claim 1

A method for processing a substrate, comprising:
providing the substrate with a plurality of first patterned structures and a trim layer underlying the first patterned structures, the plurality of first patterned structures having at least a first pitch of 36 nm or less, the first patterned structures having a first line width and first space width;
etching the trim layer utilizing the first patterned structures as a first mask to provide a plurality of trim layer structures;
after etching the trim layer, trimming the trim layer to reduce a critical dimension of the plurality of trim layer structures such that the plurality of trim layer structures have a second line width and second space width, the second line width being less than the first line width of the plurality of first patterned structures; and
utilizing the trim layer as a second mask when etching at least one layer underlying the trim layer to provide a plurality of second patterned structures in the at least one layer underlying the trim layer, a second patterned structure pitch corresponding to the first pitch.

### Claim 2 (depends on 1)

The method of claim 1, wherein the trimming the trim layer is performed with an isotropic gaseous chemical removal process.

### Claim 3 (depends on 2)

The method of claim 2, wherein the trim layer is a TEOS deposited oxide.

### Claim 4 (depends on 2)

The method of claim 2, further comprising providing an intervening planarization layer between the plurality of first patterned structures and the trim layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the trim layer is a TEOS deposited oxide.

### Claim 6 (depends on 4)

The method of claim 4, wherein portions of the intervening planarization layer remain overlying the trim layer during the isotropic gaseous chemical removal process.

### Claim 7 (depends on 6)

The method of claim 6, wherein the portions of the intervening planarization layer are removed after etching the at least one layer underlying the trim layer.

### Claim 8 (depends on 6)

The method of claim 6, wherein the portions of the intervening planarization layer are removed prior to etching the at least one layer underlying the trim layer.

### Claim 9 (depends on 4)

The method of claim 4, wherein the intervening planarization layer is removed prior to the isotropic gaseous chemical removal process.

### Claim 10

A method for processing a substrate, comprising:
providing the substrate with a plurality of first patterned structures, the plurality of first patterned structures having at least a first pitch of 36 nm or less, the first patterned structures having a first line width and first space width;
providing the substrate with a trim layer underlying the first patterned structures;
providing the substrate with an intervening layer between the plurality of first patterned structures and the trim layer;
providing the substrate with a hard mask layer underlying the trim layer;
etching the intervening layer to provide a plurality of patterned intervening layer structures corresponding to the plurality of first patterned structures;
etching the trim layer to provide a plurality of patterned trim layer structures corresponding to the plurality of first patterned structures;
after etching the trim layer, trimming the trim layer with an isotropic etch process to reduce a critical dimension of the plurality of patterned trim layer structures; and
after trimming the trim layer, etching the hard mask layer to provide a plurality of hard mask layer structures having a pitch corresponding to the first pitch but having a second line width that is less than the first line width of the plurality of first patterned structures.

### Claim 11 (depends on 10)

The method of claim 10, wherein the trimming the trim layer is performed with an isotropic gaseous chemical removal process.

### Claim 12 (depends on 11)

The method of claim 11, wherein the trim layer is a TEOS deposited oxide.

### Claim 13 (depends on 10)

The method of claim 10, wherein the intervening layer is a planarization layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the trim layer is a TEOS deposited oxide.

### Claim 15 (depends on 14)

The method of claim 14, wherein the trimming the trim layer is performed with a chemical oxide removal process and wherein portions of the intervening layer remain overlying the trim layer during the chemical oxide removal process.

### Claim 16 (depends on 15)

The method of claim 15, wherein the portions of the intervening layer are removed after etching the hard mask layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the portions of the intervening planarization layer are removed prior to etching the hard mask layer.

### Claim 18 (depends on 14)

The method of claim 14, wherein the trimming the trim layer is performed with a chemical oxide removal process and wherein the intervening layer is removed prior to the chemical oxide removal process.

### Claim 19

A method for forming a trench in a semiconductor wafer at a back end of line process step, comprising:
providing a trench pattern in an EUV resist layer on the semiconductor wafer to form a plurality of EUV resist patterned structures, the plurality of EUV resist patterned structures having at least a first pitch of 36 nm or less;
providing an intervening layer underlying the EUV resist layer, the intervening layer being a planarizing layer;
providing an oxide layer underlying the intervening layer;
providing a metal hard mask layer underlying the oxide layer;
etching the oxide layer to provide a plurality of patterned oxide layer structures corresponding to the plurality of EUV resist patterned structures;
after etching the oxide layer, performing a chemical oxide removal process on the oxide layer to reduce a line width critical dimension of the plurality of patterned oxide layer structures;
after performing the chemical oxide removal process, etching the metal hard mask layer to provide a plurality of metal hard mask layer structures having a pitch corresponding to the first pitch but having a metal hard mask line width critical dimension that corresponds to the reduced line width critical dimension of the plurality of patterned oxide layer structures; and
forming the trench in the semiconductor wafer, a trench width being larger than a space of the trench pattern due to performing the chemical oxide removal process.

### Claim 20 (depends on 19)

The method of claim 19, wherein portions of the intervening layer remain overlying the oxide layer during the chemical oxide removal process.

### Claim 21 (depends on 20)

The method of claim 20, wherein the portions of the intervening layer are removed after etching the metal hard mask.

### Claim 22 (depends on 21)

The method of claim 21, wherein the intervening layer is an organic planarization layer or a spin on hard mask layer.

### Claim 23 (depends on 20)

The method of claim 20, wherein the portions of the intervening layer are removed prior to etching the metal hard mask.

### Claim 24 (depends on 23)

The method of claim 23, wherein the intervening layer is an organic planarization layer or a spin on hard mask layer.

### Claim 25 (depends on 19)

The method of claim 19, wherein the intervening layer is removed prior to the chemical oxide removal process.

### Claim 26 (depends on 25)

The method of claim 25, wherein the intervening layer is an organic planarization layer or a spin on hard mask layer.