# US 2018/0323071 A1 · Stress Relieving Semiconductor Layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0323071 A1
- Document ID: US20180323071A1
- Status: Published application
- Kind: A1
- Application number: 16/022,939
- Filed: 2018-06-29
- Published: 2018-11-08
- Earliest claimed: 2013-05-01
- Assignees: Sensor Electronic Technology, Inc.
- Applicants: Sensor Electronic Technology, Inc.
- Inventors: Maxim S. Shatalov; Jinwei Yang; Wenhong Sun; Rakesh Jain; Michael Shur; Remigijus Gaska
- Web page: https://patentgrep.com/patent/US20180323071A1

## CPC

- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10D 48/01: Manufacture or treatment
- H10D 62/8181: {Structures having no potential periodicity in the vertical direction, e.g. lateral superlattices or lateral surface superlattices [LSS]}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3216: {Nitrides}
- H10P 14/3251: {consisting of three or more layers}
- H10P 14/3252: {Alternating layers, e.g. superlattice}
- H10P 14/3256: {Microstructure}
- H10P 14/3416: {Nitrides}
- H10H 20/01335: {the light-emitting regions comprising nitride materials}
- H10H 20/815: having stress relaxation structures, e.g. buffer layers
- H10H 20/82: Roughened surfaces, e.g. at the interface between epitaxial layers
- H10H 20/825: containing nitrogen, e.g. GaN
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/278: {Pendeoepitaxy}
- H10P 14/2901: {Materials}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS

## Abstract

A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

## Claims

### Claim 1

A structure comprising:
a substrate;
a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands; and
a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.

### Claim 2 (depends on 1)

The structure of claim 1, where in the cavity containing layer has a thickness between approximately one micron and approximately ten microns.

### Claim 3 (depends on 1)

The structure of claim 1, wherein the characteristic size of the plurality of cavities is in a range of approximately ten nanometers to approximately four thousand nanometers.

### Claim 4 (depends on 1)

The structure of claim 1, further comprising a semiconductor layer immediately adjacent to the cavity containing layer, wherein the semiconductor layer contains no large scale cavities.

### Claim 5 (depends on 4)

The structure of claim 4, wherein the semiconductor layer comprises AlxGa1-xN, wherein 0<x<1.

### Claim 6 (depends on 5)

The structure of claim 5, wherein x>0.8.

### Claim 7 (depends on 1)

The structure of claim 1, wherein a surface of the substrate adjacent to the nucleation layer is inclined at an angle.

### Claim 8 (depends on 7)

The structure of claim 7, wherein the angle is equal to or greater than 0.6 degrees and equal to or less than 3 degrees.

### Claim 9 (depends on 1)

The structure of claim 1, further comprising a second nucleation layer located directly on the nucleation layer including the plurality of nucleation islands, wherein the nucleation layer including the plurality of nucleation islands is partially-etched.

### Claim 10 (depends on 1)

The structure of claim 1, wherein the substrate is nano-patterned.

### Claim 11

A device comprising:
a substrate;
a nucleation layer located on the substrate, wherein the nucleation layer is formed of a plurality of nucleation islands;
a cavity containing layer located over the nucleation layer, wherein the cavity containing layer is formed of a semiconductor material, has a thickness greater than two monolayers, and has a plurality of cavities, and wherein the plurality of cavities have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers; and
a semiconductor layer located over the cavity containing layer, wherein the semiconductor layer contains no cavities.

### Claim 12 (depends on 11)

The device of claim 11, where in the cavity containing layer has a thickness between approximately one micron and approximately ten microns.

### Claim 13 (depends on 11)

The device of claim 11, wherein the characteristic size of the plurality of cavities is in a range of approximately ten nanometers to approximately four thousand nanometers.

### Claim 14 (depends on 11)

The device of claim 11, wherein the semiconductor layer comprises AlxGa1-xN, wherein 0<x<1.

### Claim 15 (depends on 14)

The device of claim 14, wherein x>0.8.

### Claim 16 (depends on 11)

The device of claim 11, wherein a surface of the substrate adjacent to the nucleation layer is inclined at an angle equal to or greater than 0.6 degrees and equal to or less than 3 degrees.

### Claim 17 (depends on 11)

The device of claim 11, further comprising a second nucleation layer located directly on the nucleation layer including the plurality of nucleation islands, wherein the nucleation layer including the plurality of nucleation islands is partially-etched.

### Claim 18 (depends on 11)

The device of claim 11, wherein the substrate is nano-patterned.

### Claim 19

A method comprising:
fabricating a semiconductor structure, wherein the fabricating includes:
growing a nucleation layer on a substrate, wherein the nucleation layer is formed of a plurality of nucleation islands;
forming a cavity containing layer over the nucleation layer, wherein the cavity containing layer has a thickness greater than two monolayers and a plurality of cavities; and
forming a semiconductor layer directly on the cavity containing layer, wherein the semiconductor layer comprises AlxGa1-xN, wherein 0.8<x<1.

### Claim 20 (depends on 19)

The method of claim 19, wherein the fabricating further comprises:
partially etching the nucleation layer and the substrate at a temperature of at least 1000 degrees Celsius in an H2 ambient, such that the substrate is nano-patterned; and
growing a second nucleation layer directly on the partially etched nucleation layer and the nano-patterned substrate.