# US 2018/0323066 A1 · Field-effect transistors with a body pedestal

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- Number: US 2018/0323066 A1
- Document ID: US20180323066A1
- Status: Published application
- Kind: A1
- Application number: 15/584,121
- Filed: 2017-05-02
- Published: 2018-11-08
- Earliest claimed: 2017-05-02
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Michel J. Abou-Khalil; Steven M. Shank; Alvin J. Joseph; Michael J. Zierak
- Web page: https://patentgrep.com/patent/US20180323066A1

## CPC

- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 62/364: {of IGFETs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/40: Crystalline structures
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

## Claims

### Claim 1

A structure comprising:
a first trench isolation region in a substrate, the first trench isolation region surrounding a semiconductor body; and
a body pedestal arranged in vertical alignment with the semiconductor body, the body pedestal surrounded by an undercut cavity region in the substrate that extends laterally beneath the semiconductor body.

### Claim 2 (depends on 1)

The structure of claim 1 further comprising:
a semiconductor layer on a plurality of surfaces of the first trench isolation region, the substrate, the body pedestal, and the semiconductor body that border the undercut cavity region, the semiconductor layer comprised of a polycrystalline semiconductor material.

### Claim 3 (depends on 2)

The structure of claim 2 wherein the semiconductor layer has a conformal thickness.

### Claim 4 (depends on 2)

The structure of claim 2 further comprising:
a dielectric layer between the semiconductor layer and the surfaces of the first trench isolation region, the substrate, the body pedestal, and the semiconductor body bordering the undercut cavity region.

### Claim 5 (depends on 2)

The structure of claim 2 wherein the semiconductor layer is comprised of trap-rich polysilicon.

### Claim 6 (depends on 2)

The structure of claim 2 wherein the semiconductor layer is in direct contact with the surfaces of the first trench isolation region, the substrate, the body pedestal, and the semiconductor body that border the undercut cavity region.

### Claim 7 (depends on 2)

The structure of claim 2 further comprising:
a second trench isolation region in the substrate, the second trench isolation region surrounding the first trench isolation region and the semiconductor body,
wherein the semiconductor layer includes a section that is located laterally between the first trench isolation region and the second trench isolation region.

### Claim 8 (depends on 1)

The structure of claim 1 further comprising:
a device structure formed using the semiconductor body.

### Claim 9 (depends on 8)

The structure of claim 8 wherein the device structure is a switch field-effect transistor.

### Claim 10 (depends on 1)

The structure of claim 1 wherein the undercut cavity region extends laterally beneath the first trench isolation region.

### Claim 11 (depends on 1)

The structure of claim 1 further comprising:
a well in the substrate beneath the semiconductor body,
wherein the body pedestal adjoins the well along a p-n junction located at a first depth relative to a top surface of the body pedestal, and the undercut cavity region extends vertically to a second depth that is greater than the first depth.

### Claim 12

A method comprising:
forming a first trench isolation region in a substrate, wherein the first trench isolation region surrounds a semiconductor body; and
forming an undercut cavity region in the substrate that extends laterally beneath the semiconductor body and defines a body pedestal as a first section of the substrate that is arranged in vertical alignment with the semiconductor body.

### Claim 13 (depends on 12)

The method of claim 12 further comprising:
forming a semiconductor layer on a plurality of surfaces of the first trench isolation region, the substrate, the body pedestal, and the semiconductor body that border the undercut cavity region,
wherein the semiconductor layer is comprised of a polycrystalline semiconductor material.

### Claim 14 (depends on 13)

The method of claim 13 wherein the semiconductor layer is deposited with a conformal thickness.

### Claim 15 (depends on 13)

The method of claim 13 further comprising:
before the semiconductor layer is formed, forming a dielectric layer on the surfaces of the first trench isolation region, the substrate, the body pedestal, and the semiconductor body bordering the undercut cavity region.

### Claim 16 (depends on 12)

The method of claim 12 further comprising:
forming a second trench isolation region in the substrate, wherein the second trench isolation region surrounds the first trench isolation region and the semiconductor body; and
before the undercut cavity region is formed in the substrate, removing a second section of the substrate from a space between the first trench isolation region and the second trench isolation region to open a trench.

### Claim 17 (depends on 16)

The method of claim 16 wherein the trench provides a pathway for an etching process used to form the undercut cavity region.

### Claim 18 (depends on 12)

The method of claim 12 wherein the undercut cavity region is formed by an etching process, and further comprising:
before the undercut cavity region is formed in the substrate, forming an amorphized layer in the semiconductor body,
wherein the amorphized layer is located between a top surface of the semiconductor body and the undercut cavity region such that a portion of the semiconductor body between the amorphized layer and the top surface is masked during the etching process.

### Claim 19 (depends on 18)

The method of claim 18 further comprising:
after the undercut cavity region is formed in the substrate, recrystallizing the amorphized layer in the semiconductor body.

### Claim 20 (depends on 12)

The method of claim 12 further comprising:
forming a switch field-effect transistor using the semiconductor body.