# US 2018/0322940 A1 · Memory system and operation method of the same

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- Number: US 2018/0322940 A1
- Document ID: US20180322940A1
- Status: Published application
- Kind: A1
- Application number: 15/832,205
- Filed: 2017-12-05
- Published: 2018-11-08
- Earliest claimed: 2017-05-02
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Yong-Ju Kim; Dong-Gun Kim; Do-Sun Hong
- Web page: https://patentgrep.com/patent/US20180322940A1

## CPC

- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G11C 2211/4062: Parity or ECC in refresh operations
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for operating a memory system includes: reading a data from a memory device; detecting and correcting an error of the data; when the error of the data is equal to or greater than a threshold value, deciding an address corresponding to memory cells from which the data is read in the memory device as a rewrite-requiring address; and rewriting the data of the memory cell corresponding to the rewrite-requiring address.

## Claims

### Claim 1

A method for operating a memory system, comprising:
reading a data from a memory device;
detecting and correcting an error of the data;
when the error of the data is equal to or greater than a threshold value, deciding an address corresponding to memory cells from which the data is read in the memory device as a rewrite-requiring address; and
rewriting the data of the memory cells corresponding to the rewrite-requiring address.

### Claim 2 (depends on 1)

The method of claim 1, wherein the reading of the data, the detecting and correcting of the error of the data, and the deciding of the address corresponding to the memory cells are performed upon a request from a host.

### Claim 3 (depends on 1)

The method of claim 1, wherein the rewriting of the data of the memory cells includes:
reading the data of the memory cells corresponding to the rewrite-requiring address;
detecting and correcting an error of the read data so as to produce an error-corrected data; and
writing the error-corrected data in the memory cells corresponding to the rewrite-requiring address.

### Claim 4 (depends on 3)

The method of claim 3, wherein the rewriting of the data of the memory cells includes
when it is impossible to correct the error of the read data, repeatedly changing a voltage level of a read voltage that is used in the memory device and performing the operation of reading the data of the memory cells corresponding to the rewrite-requiring address.

### Claim 5 (depends on 1)

The method of claim 1, wherein the reading of the data, the detecting and correcting of the error of the data, and the deciding of the address corresponding to the memory cells are performed periodically while changing the memory cells from which the data is read, when the error of the data is equal to or greater than a threshold value.

### Claim 6 (depends on 1)

The method of claim 1, wherein the memory device includes a plurality of memory cells, and
each of the plurality of the memory cells includes a resistive memory element and a selection element.

### Claim 7 (depends on 6)

The method of claim 6, wherein the resistive memory element includes a phase-change memory device.

### Claim 8

A memory system, comprising:
a memory device including a plurality of memory cells; and
a memory controller suitable for reading a data from the memory device, and when an error of the data is equal to or greater than a threshold value, deciding an address corresponding to memory cells from which the data is read as a rewrite-requiring address.

### Claim 9 (depends on 8)

The memory system of claim 8, wherein the memory controller rewrites the data of the memory cells corresponding to the rewrite-requiring address.

### Claim 10 (depends on 8)

The memory system of claim 8, wherein the memory controller reads the data from the memory device in response to a read operation request from a host, and
when an error of the data is equal to or greater than a threshold value, the memory controller performs an operation of deciding the address corresponding to the memory cells from which the data is read as the rewrite-requiring address.

### Claim 11 (depends on 8)

The memory system of claim 8, wherein the memory controller reads the data from the memory device, and
when an error of the data is equal to or greater than a threshold value, the memory controller periodically performs the operation of deciding the address corresponding to the memory cells from which the data is read as the rewrite-requiring address while changing the memory cells from which the data is read.

### Claim 12 (depends on 9)

The memory system of claim 9, wherein during the rewrite operation, the memory controller reads the data from the memory cells of the memory device corresponding to the rewrite-requiring address, detects and corrects an error of the data so as to produce an error-corrected data, and writes the error-corrected data in the memory cells of the memory device corresponding to the rewrite-requiring address.

### Claim 13 (depends on 12)

The memory system of claim 12, wherein during the rewrite operation, when it is impossible to correct the error of the read data, the memory controller periodically performs an operation of reading the data from the memory cells corresponding to the rewrite-requiring address while changing a voltage level of a read voltage that is used in the memory device until the error of the read data becomes correctable.

### Claim 14 (depends on 9)

The memory system of claim 9, wherein the memory controller includes:
an error-correction circuit suitable for detecting and correcting an error of the data read from the memory device so as to produce an error-corrected data;
a rewrite-requiring address storing circuit suitable for storing the rewrite-requiring address; and
a rewrite circuit suitable for rewrite the data of the memory cell corresponding to the rewrite-requiring address.

### Claim 15 (depends on 14)

The memory system of claim 14, wherein the memory controller includes:
a host interface suitable for communication with a host;
a scheduler suitable for deciding a process order of requests of the host;
a command generator suitable for generating a command to be applied to the memory device;
a memory interface suitable for communication with the memory device; and
a read retry circuit suitable for controlling a read retry operation of the memory device.

### Claim 16 (depends on 8)

The memory system of claim 8, wherein each of plurality of the memory cells includes:
a resistive memory element; and
a selection element.

### Claim 17 (depends on 16)

The memory system of claim 16, wherein the resistive memory element is a phase-change memory device.