# US 2018/0322938 A1 · Semiconductor apparatus for compensating for degradation and semiconductor system using the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322938 A1 - Document ID: US20180322938A1 - Status: Published application - Kind: A1 - Application number: 15/845,343 - Filed: 2017-12-18 - Published: 2018-11-08 - Earliest claimed: 2017-05-02 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Woongrae KIM; Bok Rim KO; Keun Soo SONG - Web page: https://patentgrep.com/patent/US20180322938A1 ## CPC - G11C 29/50004: {of threshold voltage} - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/12005: {comprising voltage or current generators} - H03K 5/159: Applications of delay lines not covered by the preceding subgroups - G11C 29/50012: {of timing} - G11C 2029/0401: {in embedded memories} - G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information} - H03K 2005/00019: {Variable delay} - G11C: STATIC STORES (semiconductor memory devices H10B) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage. ## Claims ### Claim 1 A semiconductor apparatus comprising: a degradation detection circuit configured for detecting degradation that has occurred in a semiconductor apparatus and generating degradation information; a voltage generator configured for generating a variable bias voltage and a variable gate voltage based on the degradation information; and a circuit block including at least one transistor, the at least one transistor configured to operate by receiving the variable bias voltage and the variable gate voltage. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein the degradation detection circuit comprises: a degradation-insensitive delay path configured for delaying a pulse signal by a delay amount according to a variation in process, temperature and voltage, and generating a first delayed signal; a degradation-sensitive delay path configured for delaying the pulse signal by a delay amount according to a variation in process, temperature and voltage and a degradation of the semiconductor apparatus, and generating a second delayed signal; and a detector configured for comparing a phase difference of the first and second delayed signals, and generating the degradation information. ### Claim 3 (depends on 2) The semiconductor apparatus according to claim 2, wherein the semiconductor apparatus performs an active operation and a standby operation, and wherein the degradation-insensitive delay path is turned on during the standby operation, and the degradation-sensitive delay path is turned on during the active operation and the standby operation. ### Claim 4 (depends on 1) The semiconductor apparatus according to claim 1, wherein the voltage generator changes levels of the variable bias voltage and the variable gate voltage based on the degradation information, and a unit amount of change of the variable gate voltage is smaller than a unit amount of change of the variable bias voltage. ### Claim 5 (depends on 1) The semiconductor apparatus according to claim 1, wherein the degradation detection circuit comprises: a degradation-insensitive delay path configured for delaying a pulse signal by a first delay amount and generating a first delayed signal; a degradation-sensitive delay path configured for delaying a pulse signal by a second delay amount and generating a second delayed signal; a detector configured for comparing a phase difference of the first and second delayed signals, and generating the degradation information, wherein the first delay amount and the second delay amount are influenced by the degradation of the semiconductor apparatus and the first delay amount is influenced less than the second delay amount is influenced by the degradation of the semiconductor apparatus. ### Claim 6 (depends on 1) The semiconductor apparatus according to claim 1, wherein the circuit block comprises: a logic circuit; and a power gating circuit including a first sleep transistor, the first sleep transistor coupled between a first power supply voltage and the logic circuit. ### Claim 7 (depends on 6) The semiconductor apparatus according to claim 6, wherein the power gating circuit further includes a second sleep transistor, the second sleep transistor coupled between a second power supply voltage and the logic circuit. ### Claim 8 (depends on 7) The semiconductor apparatus according to claim 7, wherein the variable bias voltage includes a first variable bias voltage and a second variable bias voltage, and the variable gate voltage includes a first variable gate voltage and a second variable gate voltage, wherein the first variable bias voltage is applied to a body of the first sleep transistor, and the second variable bias voltage is applied to a body of the second sleep transistor, and wherein the first variable gate voltage is applied to a gate of the first sleep transistor, and the second variable gate voltage is applied to a gate of the second sleep transistor. ### Claim 9 A semiconductor system comprising: a memory apparatus configured for detecting degradation that has occurred in the memory apparatus and generating degradation information based on a training command, and generating a variable bias voltage and a variable gate voltage based on a voltage setting command; and a memory controller configured for providing the training command to the memory apparatus, and generating the voltage setting command based on the degradation information. ### Claim 10 (depends on 9) The semiconductor system according to claim 9, wherein the memory apparatus comprises: a command path configured for generating a degradation detection signal based on the training command, and generating a voltage control signal based on the voltage setting command; a degradation detection circuit configured for detecting a degradation occurred in the memory apparatus based on the degradation detection signal, and generating the degradation information; and a voltage generator configured for generating the variable bias voltage and the variable gate voltage based on the voltage control signal. ### Claim 11 (depends on 10) The semiconductor system according to claim 10, wherein the degradation detection circuit comprises: a degradation-insensitive delay path configured for delaying a pulse signal by a delay amount according to a variation in process, temperature and voltage, and generating a first delayed signal; a degradation-sensitive delay path configured for delaying the pulse signal by a delay amount according to a variation in process, temperature and voltage and a degradation occurred in the memory apparatus, and generating a second delayed signal; and a detector configured for comparing a phase difference of the first and second delayed signals, and generating the degradation information. ### Claim 12 (depends on 10) The semiconductor system according to claim 10, wherein the voltage generator changes levels of the variable bias voltage and the variable gate voltage based on the degradation information, and a unit amount of change of the variable gate voltage is smaller than a unit amount of change of the variable bias voltage. ### Claim 13 (depends on 10) The semiconductor system according to claim 10, wherein the degradation detection circuit comprises: a degradation-insensitive delay path configured for delaying a pulse signal by a first delay amount and generating a first delayed signal; a degradation-sensitive delay path configured for delaying a pulse signal by a second delay amount and generating a second delayed signal; a detector configured for comparing a phase difference of the first and second delayed signals, and generating the degradation information, wherein the first delay amount and the second delay amount are influenced by the degradation of the semiconductor apparatus and the first delay amount is influenced less than the second delay amount is influenced by the degradation of the semiconductor apparatus. ### Claim 14 (depends on 10) The semiconductor system according to claim 10, wherein the memory apparatus further comprises: a logic circuit; and a power gating circuit including at least one sleep transistor, the first sleep transistor configured to couple a power supply voltage and the logic circuit. ### Claim 15 (depends on 14) The semiconductor system according to claim 14, wherein the variable bias voltage is applied to a body of the sleep transistor, and the variable gate voltage is applied to a gate of the sleep transistor. ### Claim 16 (depends on 10) The semiconductor system according to claim 10, wherein the memory apparatus further comprises: a data buffer configured for transmitting the degradation information to the memory controller. ### Claim 17 (depends on 9) The semiconductor system according to claim 9, wherein the memory controller comprises: a training circuit configured for generating a training signal to perform a training with the memory apparatus, and generating a voltage setting control signal based on the degradation information; and a control circuit configured for generating the training command based on the training signal, and generating the voltage setting command based on the voltage setting control signal. ### Claim 18 A semiconductor apparatus comprising: a circuit block including at least one transistor configured to receive a variable bias voltage and a variable gate voltage; and a degradation detection circuit configured to compensate for a variation in a threshold voltage of the at least one transistor by generating degradation information to change levels of the variable bias voltage and the variable gate voltage being received by the at least one transistor. ### Claim 19 (depends on 18) The semiconductor apparatus according to claim 18, wherein the level of the variable bias voltage is changed prior to the variable gate voltage being changed.