# US 2018/0322937 A1 · Apparatuses and methods including nested mode registers

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- Number: US 2018/0322937 A1
- Document ID: US20180322937A1
- Status: Published application
- Kind: A1
- Application number: 16/033,076
- Filed: 2018-07-11
- Published: 2018-11-08
- Earliest claimed: 2016-07-20
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kallol Mazumder; William O'Leary
- Web page: https://patentgrep.com/patent/US20180322937A1

## CPC

- G11C 29/16: using microprogrammed units, e.g. state machines
- G06F 11/267: Reconfiguring circuits for testing, e.g. LSSD, partitioning
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/109: {Control signal input circuits}
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/10: Decoders
- G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation
- H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)}
- G11C 8/06: Address interface arrangements, e.g. address buffers
- G11C 29/46: Test trigger logic
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.

## Claims

### Claim 1

A method comprising:
storing, in a mode register, mode register data and address information;
decoding, with a decoder circuit, the address information to identify a nested mode register; and
responsive to identifying the nested mode register, storing the mode register data in the nested mode register.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
responsive to identifying the nested mode register, providing an enable signal to the nested mode register.

### Claim 3 (depends on 1)

The method of claim 1, wherein the set of mode register data are stored in the mode register responsive to receiving a mode register set command.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
storing select information in the mode register, wherein the select information indicates that the mode register data is to be written to the identified nested mode register.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
storing second select information in the mode register; and
providing the mode register data from the identified nested mode register based, at least in part, on the second select information.

### Claim 6 (depends on 5)

The method of claim 5, wherein the mode register data is provided in conjunction with additional mode register data from a plurality of additional nested mode registers.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
providing, by a select circuit coupled to the nested mode register, the mode register data stored in the nested mode register.

### Claim 8 (depends on 7)

The method of claim 7, wherein the mode register data is provided in conjunction with additional mode register data from a plurality of additional nested mode registers responsive to second select information stored in the mode register.

### Claim 9 (depends on 1)

The method of claim 1, wherein the mode register data is provided in conjunction with additional mode register data from a plurality of additional nested mode registers coupled in pairs to respective multiplexers of a plurality of multiplexers,

### Claim 10 (depends on 9)

The method of claim 9, wherein a select circuit coupled to the mode register includes the plurality of multiplexers configured to provide the mode register data in conjunction with additional mode register data responsive to second select information received from the mode register.

### Claim 11

A method comprising:
storing, in a mode register, mode register address information and mode register data;
decoding, with a decoder circuit, the mode register address information to identify a second mode register of a plurality of second mode registers;
providing an enable signal to the identified second mode register; and
responsive to providing the enable signal, storing the mode register data in the identified second mode register.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
storing, in the mode register, select information, wherein a select circuit is configured to provide the mode register data from the identified mode register responsive to the select information.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
providing the mode register data stored on a subset of the plurality of second mode registers responsive to the select information.

### Claim 14 (depends on 13)

The method of claim 13, wherein the subset of the plurality of second mode registers includes the identified mode register.

### Claim 15 (depends on 13)

The method of claim 13, wherein the mode register data is provided on a data bus of a memory device.

### Claim 16 (depends on 11)

The method of claim 11, wherein each second mode register of the plurality of second mode registers is configured to store eight bits.

### Claim 17

A method comprising:
receiving, by a first mode register, a mode register set command;
storing mode register data and mode register address information in the first mode register based on the received mode register set command;
selectively enabling, by a decoder circuit responsive to receiving the mode register address information from the first mode register, a second mode register among a plurality of second mode registers to store the mode register data.

### Claim 18 (depends on 17)

The method of claim 17, wherein the mode register data stored in the second mode register is provided by a select circuit coupled to the second mode register.

### Claim 19 (depends on 18)

The method of claim 18, wherein the mode register data is provided by the select circuit based on selection information stored in the first mode register.

### Claim 20 (depends on 17)

The method of claim 17, wherein the mode register data stored in the second mode register is provided by the select circuit by using a plurality of multiplexers included in the select circuit.