# US 2018/0322935 A1 · Word line dependent pass voltages in non-volatile memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322935 A1 - Document ID: US20180322935A1 - Status: Published application - Kind: A1 - Application number: 16/032,557 - Filed: 2018-07-11 - Published: 2018-11-08 - Earliest claimed: 2016-07-07 - Assignees: SanDisk Technologies LLC - Applicants: SanDisk Technologies LLC - Inventors: Xiying Costa - Web page: https://patentgrep.com/patent/US20180322935A1 ## CPC - G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/28: using differential sensing or reference cells, e.g. dummy cells - G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed. ## Claims ### Claim 1 An apparatus, comprising: a plurality of word lines coupled to a plurality of memory cells connected in series; and a program verification circuit, the program verification circuit configured to apply a first pass voltage to a previously programmed word line to verify a first selected word line and configured to apply a second pass voltage to the previously programmed word line to verify a second selected word line, the second pass voltage is higher than the first pass voltage and the second selected word line is programmed subsequent to the first selected word line. ### Claim 2 (depends on 1) The apparatus of claim 1, further comprising: a source select gate coupled to the plurality of memory cells; and wherein the previously programmed word line is between the first selected word line and the source select gate; and wherein the first selected word line is positioned between the second selected word line and the source select gate. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein: the previously programmed word line is a first previously programmed word line; the program verification circuit applies the first pass voltage to a second previously programmed word line to verify the first selected word line; and the program verification circuit applies the second pass voltage to the second previously programmed word line to verify the second selected word line. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein: the program verification circuit applies a third pass voltage to the previously programmed word line to verify a third selected word line of the plurality; the third pass voltage is higher than the second pass voltage; and the third selected word line is programmed subsequent to the second selected word line. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein: the previously programmed word line is a first previously programmed word line; the program verification circuit verifies the first selected word line by applying a verify voltage to the first selected word line and applying the first pass voltage to a first set of previously programmed word lines including the first previously programmed word line; and the program verification circuit verifies the second selected word line by applying the verify voltage to the second selected word line and applying the second pass voltage to a second set of previously programmed word lines, the second set of previously programmed word lines includes the first set of previously programmed word lines and one or more additional previously programmed word lines. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein: the program verification circuit applies a third pass voltage to an unprogrammed word line of the plurality to verify the first selected word line, the third pass voltage is lower than the first pass voltage; and the program verification circuit applies a fourth pass voltage to the unprogrammed word line to verify the second selected word line, the fourth pass voltage is higher than the third pass voltage and lower than the first pass voltage. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein: the program verification circuit applies the first pass voltage to the previously programmed word line while applying a first verify voltage to the first selected word line; the program verification circuit applies the second pass voltage to the previously programmed word line while applying the first verify voltage to the second selected word line; the program verification circuit applies a third pass voltage to the previously programmed word line while applying a second verify voltage to the first selected word line, the second verify voltage is higher than the first verify voltage, the first pass voltage is higher than the third pass voltage; and the program verification circuit applies a fourth pass voltage to the previously programmed word line while applying the second verify voltage to the second selected word line, the fourth pass voltage is higher than the third pass voltage and lower than the second pass voltage. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein: the plurality of memory cells is part of a non-volatile memory array; the non-volatile memory array is arranged in a three dimensional structure; and the plurality of non-volatile memory cells is arranged as a NAND string. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the plurality of memory cells are part of a first NAND string and the apparatus further includes one or more additional NAND strings coupled to the plurality of word lines. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the program verification circuit includes a sense amplifier circuit and the apparatus further comprises: a bit line whereby the plurality of memory cells is connected to the sense amplifier circuit; and a drain select gate through which the bit line is coupled to the plurality of memory cells. ### Claim 11 A method, comprising: applying a first pass voltage to two or more word lines positioned between a selected word line and a select gate during program verification if the selected word line is in a first zone of word lines; and applying a second pass voltage to two or more word lines positioned between the selected word line and the select gate during program verification if the selected word line is in a second zone of word lines, the second pass voltage is higher than the first pass voltage, the first zone is positioned between the second zone and the select gate, and each of the word lines connected to a corresponding one of a group of memory cells connected in series and coupled to the select gate. ### Claim 12 (depends on 11) The method of claim 11, further comprising: applying a third pass voltage to first and second adjacent word lines of the selected word line during program verification if the selected word line is in the first zone, the third pass voltage is higher than the second pass voltage; and applying the third pass voltage to the first and second adjacent word lines during program verification if the selected word line is in the second zone. ### Claim 13 (depends on 12) The method of claim 12, further comprising: applying a first verify voltage to the selected word line while applying the first pass voltage if the selected word line is in the first zone; applying the first verify voltage to the selected word line while applying the second pass voltage if the selected word line is in the second zone; applying a second verify voltage to the selected word line while applying a fourth pass voltage to the two or more word lines if the selected word line is in the first zone, the second verify voltage is higher than the first verify voltage, the first pass voltage is higher than the fourth pass voltage; and applying the second verify voltage to the selected word line while applying a fifth pass voltage to the two or more word lines if the selected word line is in the second zone, the fifth pass voltage is higher than the fourth pass voltage and lower than the second pass voltage. ### Claim 14 (depends on 11) The method of claim 11, further comprising: programming the two or more word lines; and programming the selected word line after programming the two or more word lines; wherein the two or more word lines are two are more word lines that are subjected to programming after erase and prior to programming the selected word line; and wherein programming for the first zone of word lines begins prior to programming for the second zone of word lines. ### Claim 15 (depends on 11) The method of claim 11, wherein the group of memory cells are part of a first NAND string and each of the word lines are further connected to one or more additional NAND strings. ### Claim 16 (depends on 11) The method of claim 11, wherein the select gate is a source side select gate. ### Claim 17 An apparatus, comprising: a source line; a plurality of word lines each connected to a corresponding one of a group of memory cells connected in series; means for applying to an unselected word line between the source line and a selected word line a first pass voltage based at least in part on applying a verify voltage to a first selected word line, wherein the first selected word line is in a first zone of word lines of the plurality; means for applying to the unselected word line a second pass voltage based at least in part on applying the verify voltage to a second selected word line, wherein the second selected word line is in a second zone of word lines of the plurality, the second pass voltage is higher than the first pass voltage, the first zone is between the second zone and the source line and is programmed before the second zone; and means for applying to the unselected word line a third pass voltage based at least in part on applying the verify voltage to a third selected word line, wherein the third selected word line is in a third zone of word lines of the plurality, the third pass voltage is higher than the second pass voltage, the second zone is between the third zone and the first zone and is programmed before the third zone. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the unselected word line is a first unselected word line, the apparatus further comprising: a bit line; means for applying to a second unselected word line between the bit line and the selected word line a fourth pass voltage based at least in part on applying the verify voltage if the selected word line is in the first zone, the fourth pass voltage is lower than the first pass voltage; means for applying to the second unselected word line a fifth pass voltage based at least in part on applying the verify voltage if the selected word line is in the second zone, the fifth pass voltage is lower than the second pass voltage and higher than the fourth pass voltage; and means for applying to the second unselected word line a sixth pass voltage based at least in part on applying the verify voltage if the selected word line is in the third zone, the sixth pass voltage is lower than the third pass voltage and higher than the fifth pass voltage. ### Claim 19 (depends on 17) The apparatus of claim 17, wherein the group of memory cells are part of a first NAND string and the apparatus further includes one or more additional NAND strings coupled to the plurality of word lines. ### Claim 20 (depends on 17) The apparatus of claim 17, wherein the group of memory cells is part of a non-volatile memory array, and the non-volatile memory array is arranged in a three dimensional structure.