# US 2018/0322933 A1 · Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322933 A1 - Document ID: US20180322933A1 - Status: Published application - Kind: A1 - Application number: 16/035,857 - Filed: 2018-07-16 - Published: 2018-11-08 - Earliest claimed: 2012-04-03 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Akira Goda; Yijie Zhao; Krishna Parat - Web page: https://patentgrep.com/patent/US20180322933A1 ## CPC - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices. ## Claims ### Claim 1 A memory device, comprising: a first data line selectively connected to a first end of a first string of series-connected memory cells; a second data line selectively connected to a first end of a second string of series-connected memory cells; and a controller, wherein the controller is configured to cause the memory device to perform a method comprising: applying a first voltage level to the first data line while applying a second voltage level, higher than the first voltage level, to the second data line; and while applying the first voltage level to the first data line and while applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of the first string of series-connected memory cells selected for programming; wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming; and wherein the first voltage level is a positive voltage level. ### Claim 2 (depends on 1) The memory device of claim 1, further comprising: a first select gate connected in series between the first end of the first string of series-connected memory cells and the data line; and a second select gate connected in series between the first end of the second string of series-connected memory cells and the data line; wherein the method the controller is configured to cause the memory device to perform further comprises: applying a fourth voltage level to a control gate of the second select gate while applying the first voltage level to the first data line and while applying the second voltage level to the second data line; wherein the first voltage level is higher than or equal to the fourth voltage level. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the method the controller is configured to cause the memory device to perform further comprises applying a fifth voltage level to a control gate of the first select gate while applying the first voltage level to the first data line and while applying the second voltage level to the second data line, wherein the fifth voltage level is higher than the first voltage level. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the third voltage level applied to the particular access line while applying the second voltage level to the second data line and while applying the fourth voltage level to the control gate of the second select gate is configured to inhibit a threshold voltage of a memory cell of the second string of series-connected memory cells coupled to the particular access line. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the method the controller is configured to cause the memory device to perform further comprises applying a respective voltage level to each remaining access line coupled to any memory cell of the first string of series-connected memory cells not selected for programming while applying the third voltage level to the particular access line, wherein the respective voltage levels applied to each remaining access line coupled to any memory cell of the first string of series-connected memory cells not selected for programming are each lower than the third voltage level. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the respective voltage level applied to a particular remaining access line coupled to a memory cell of the first string of series-connected memory cells not selected for programming is different than the respective voltage level applied to a different remaining access line coupled to a memory cell of the first string of series-connected memory cells not selected for programming. ### Claim 7 A memory device, comprising: a first select gate connected in series between a first data line and a first end of a first string of series-connected memory cells; a second select gate connected in series between a second data line and a first end of a second string of series-connected memory cells; a third select gate connected in series between a source and a second end of the first string of series-connected memory cells; a fourth select gate connected in series between the source and the second end of the second string of series-connected memory cells; and a controller, wherein the controller is configured to cause the memory device to perform a method comprising: applying a positive first voltage level to the first data line while applying a second voltage level, higher than the first voltage level, to the second data line; and applying a third voltage level to a particular access line coupled to a memory cell of the first string of series-connected memory cells selected for programming while applying the first voltage level to the first data line and while applying the second voltage level to the second data line; applying a fourth voltage level to a control gate of the second select gate while applying the first voltage level to the first data line and while applying the second voltage level to the second data line; wherein the first voltage level is higher than or equal to the fourth voltage level; wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming; and wherein the third voltage level applied to the particular access line while applying the second voltage level to the second data line and while applying the fourth voltage level to the control gate of the second select gate is configured to inhibit increasing a threshold voltage of a memory cell of the second string of series-connected memory cells coupled to the particular access line. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the method the controller is configured to cause the memory device to perform further comprises applying a fifth voltage level to the source while applying the first voltage level to the first data line and while applying the second voltage level to the second data line, wherein the first voltage level is higher than or equal to the fifth voltage level. ### Claim 9 (depends on 7) The memory device of claim 7, wherein the method the controller is configured to cause the memory device to perform further comprises applying a fifth voltage level to the source while applying the first voltage level to the first data line and while applying the second voltage level to the second data line, wherein the fifth voltage level is higher than the first voltage level. ### Claim 10 (depends on 8) The memory device of claim 8, wherein the method the controller is configured to cause the memory device to perform further comprises: applying a sixth voltage level to a control gate of the third select gate while applying the fifth voltage level to the source; applying a seventh voltage level to a control gate of the fourth select gate while applying the fifth voltage level to the source; wherein the sixth voltage level is lower than or equal to the fifth voltage level; and wherein the seventh voltage level is lower than or equal to the fifth voltage level. ### Claim 11 (depends on 7) The memory device of claim 7, wherein the method the controller is configured to cause the memory device to perform further comprises applying a fourth voltage level, higher than the first voltage level, to a control gate of the first select gate while applying the first voltage level to the first data line and while applying the second voltage level to the second data line, and applying a fifth voltage level, lower than or equal to the first voltage level, to a control gate of the second select gate while applying the first voltage level to the first data line and while applying the second voltage level to the second data line. ### Claim 12 An electronic system, comprising: a communications interface; a memory access device coupled to the communications interface; and a memory device coupled to the communications interface, the memory device comprising: a first data line selectively connected to a first end of a first string of series-connected memory cells; a second data line selectively connected to a first end of a second string of series-connected memory cells; and a controller, wherein the controller is configured to cause the memory device to perform a method comprising: applying a positive first voltage level to the first data line while applying a second voltage level, higher than the first voltage level, to the second data line; connecting the first data line to the first end of the first string of series-connected memory cells while applying the first voltage level to the first data line and while applying a second voltage level to the second data line; isolating the second data line from the first end of the second string of series-connected memory cells while connecting the first data line to the first end of the first string of series-connected memory cells; applying a third voltage level to a particular access line coupled to a memory cell of the first string of series-connected memory cells selected for programming while connecting the first data line to the first end of the first string of series-connected memory cells and while isolating the second data line from the first end of the second string of series-connected memory cells; wherein the third voltage level applied to the particular access line is configured to increase a threshold voltage of the memory cell selected for programming while connecting the first data line to the first end of the first string of series-connected memory cells; and wherein the third voltage level applied to the particular access line is configured to inhibit increasing a threshold voltage of a memory cell of the second string of series-connected memory cells coupled to the particular access line while isolating the second data line from the first end of the second string of series-connected memory cells. ### Claim 13 (depends on 12) The electronic system of claim 12, wherein the first voltage level is higher than or equal to 0.5V. ### Claim 14 (depends on 13) The electronic system of claim 13, wherein the first voltage level is lower than or equal to 1V. ### Claim 15 (depends on 12) The electronic system of claim 12, wherein the method the controller is configured to cause the memory device to perform further comprises applying a voltage level to a first select gate connected in series between the first data line and the first end of the first string of series-connected memory cells that is higher than the first voltage level to connect the first data line to the first end of the first string of series-connected memory cells. ### Claim 16 (depends on 15) The electronic system of claim 15, wherein the method the controller is configured to cause the memory device to perform further comprises applying a voltage level to a second select gate connected in series between the second data line and the first end of the second string of series-connected memory cells that is lower than or equal to the second voltage level to isolate the second data line from the first end of the second string of series-connected memory cells. ### Claim 17 (depends on 16) The electronic system of claim 16, wherein the method the controller is configured to cause the memory device to perform further comprises applying a voltage level to the second select gate that is lower than or equal to the first voltage level to isolate the second data line from the first end of the second string of series-connected memory cells. ### Claim 18 (depends on 16) The electronic system of claim 16, wherein the voltage level applied to the first select gate is lower than the second voltage level, and wherein the voltage level applied to the second select gate is lower than or equal to the first voltage level. ### Claim 19 (depends on 12) The electronic system of claim 12, wherein the method the controller is configured to cause the memory device to perform further comprises isolating a second end of the first string of series-connected memory cells from a source and isolating a second end of the second string of series-connected memory cells from the source while connecting the first data line to the first end of the first string of series-connected memory cells and while isolating the second data line from the first end of the second string of series-connected memory cells. ### Claim 20 (depends on 12) The electronic system of claim 12, wherein the method the controller is configured to cause the memory device to perform further comprises isolating the second end of the first string of series-connected memory cells from the source while applying a voltage level to the source that is lower than or equal to the first voltage level.