# US 2018/0322928 A1 · Loop control strobe skew > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322928 A1 - Document ID: US20180322928A1 - Status: Published application - Kind: A1 - Application number: 15/589,120 - Filed: 2017-05-08 - Published: 2018-11-08 - Earliest claimed: 2017-05-08 - Assignees: SanDisk Technologies LLC - Applicants: Sandisk Technologies LLC - Inventors: Kenneth Louie; Qui Nguyen; Tai-yuan Tseng; Jong Yuh; Ohwon Kwon - Web page: https://patentgrep.com/patent/US20180322928A1 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 11/5671: {using charge trapping in an insulator} - G11C 16/10: Programming or data input circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 2211/562: Multilevel memory programming aspects - G11C 2211/5621: Multilevel programming verification - G11C 2211/563: Multilevel memory reading aspects - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract This disclosure provides a method and apparatus for applying a dynamic strobe signal to a plurality of sense modules during programming of an array of memory cells, where a characteristic of the dynamic strobe signal is configured to limit a peak current level through the plurality of sense modules. An example apparatus the array of memory cells, a plurality of bit lines spanning the array of memory cells, and the plurality of sense modules connected to the bit lines. The plurality of sense modules enable sensing of states of memory cells. A controller determines the characteristic of the dynamic strobe signal, where the dynamic strobe signal is varied based on the determined characteristic. ## Claims ### Claim 1 An apparatus comprising: an array of memory cells; a plurality of bit lines spanning the array of memory cells; a plurality of sense modules connected to the bit lines, the plurality of sense modules configured to enable sensing of states of memory cells; and a controller, the controller configured to: apply programming pulses to the array of memory cells; determine a characteristic of a dynamic strobe signal, the characteristic configured to limit a peak current level through the plurality of sense modules; and apply the dynamic strobe signal to the plurality of sense modules to sense, via the bit lines, a state of the memory cells, wherein the dynamic strobe signal varies based on the determined characteristic of the dynamic strobe signal. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the characteristic for the dynamic strobe signal comprises a first number of sense modules to which the dynamic strobe signal is to be applied at a first time, and wherein the first number of sense modules comprises a first subset of the plurality of sense modules. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the first number of sense modules is based on a program loop number of the programming pulses, and wherein each of the programming pulses are part of a programming sequence and have a unique program loop number. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein application of the dynamic strobe signal comprises application of the dynamic strobe signal to an increasing number of the plurality of sense modules as the programming sequence proceeds. ### Claim 5 (depends on 2) The apparatus of claim 2, wherein the number of sense modules is based on a predicted peak current of the dynamic strobe signal. ### Claim 6 (depends on 2) The apparatus of claim 2, wherein the characteristic of the dynamic strobe signal further comprises a second number of sense modules to which the dynamic strobe signal is to be applied at a second time, wherein the second number of sense modules comprises a second subset of the plurality of sense modules, and wherein the controller is further configured to: apply the dynamic strobe signal to the first subset of sense modules associated with a first subset of memory cells after a first programming pulse; and apply the dynamic strobe signal to the second subset of sense modules associated with a second subset of memory cells after a second programming pulse. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the second subset of memory cells comprises a larger number of memory cells than the first subset of memory cells. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the first subset of memory cells are locked out at the second time. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the characteristic of the dynamic strobe signal comprises a first pulse width of a first portion of the dynamic strobe signal applied at a first time and a second pulse width of a second portion of the strobe signal applied at second time, and wherein the first pulse width and the second pulse width are of different durations of time. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the characteristic of the dynamic strobe signal comprises a variable strobe skew for the dynamic strobe signal. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the characteristic of the dynamic strobe signal is a measurement of the peak current flowing to the plurality of sense modules via the dynamic strobe signal. ### Claim 12 A non-transitory computer readable medium having instructions thereon that, upon execution by a computing device, cause the computing device to perform operations comprising: applying a first programming pulse to an array of memory cells; determining a first subset of memory cells to sense based on a predetermined condition, the first subset of memory cells configured to limit a peak current of a dynamic strobe signal below a predetermined threshold during a sense operation; sensing a state of the first subset of memory cells by applying the dynamic strobe signal to an associated first subset of sense modules, wherein the first subset of sense modules is connected to a plurality of bit lines spanning the array; and applying a second programming pulse to the array of memory cells. ### Claim 13 (depends on 12) The non-transitory computer readable medium of claim 12, wherein each of the memory cells comprises transistors that are configured to be programmed to one of sixteen states. ### Claim 14 (depends on 12) The non-transitory computer readable medium of claim 12, wherein the instructions further cause the computing device to perform operations comprising: determining a second subset of memory cells to sense based on the predetermined condition; and sensing, after the second programming pulse, the second subset of memory cells by applying the dynamic strobe signal to an associated second subset of the sense modules. ### Claim 15 (depends on 14) The non-transitory computer readable medium of claim 14, wherein the predetermined condition comprises whether memory cells are in an erase state such that the first subset of memory cells comprises memory cells in an erase state. ### Claim 16 (depends on 15) The non-transitory computer readable medium of claim 15, wherein the second subset of memory cells comprises memory cells in a non-erase state. ### Claim 17 (depends on 12) The non-transitory computer readable medium of claim 12, wherein the predetermined condition comprises a program loop count of a plurality of programming pulses. ### Claim 18 A method comprising: applying a first programming pulse to an array of memory cells along wordlines of the array; sensing, after applying the first programming pulse, a state of a first group of the memory cells associated with a first group of latches, wherein the first group is determined based at least in part on a program loop count or type of the first programming pulse; applying a second programming pulse to the array of memory cells; sensing, after applying the second programming pulse, a state of a second group of the memory cells associate with a second group of latches, wherein the second group of latches comprises a different number of latches than the first group of latches. ### Claim 19 (depends on 18) The method of claim 18, wherein the first and second groups of memory cells are determined to limit a peak current of a signal used to sense the first and second groups of memory cells below a predetermined threshold. ### Claim 20 (depends on 18) The method of claim 18, wherein the first and second groups of memory cells are determined based on at least one of: a program loop count of a plurality of programming pulses or a type of programming pulse applied to the array of memory cells. ### Claim 21 (depends on 18) The method of claim 18, wherein the first and second groups of memory cells are determined based on at least one of: a known state of the memory cells or a measured peak current of the dynamic strobe signal. ### Claim 22 An apparatus comprising: means for applying a first programming pulse to an array of memory cells along wordlines of the array; means for determining a first pulse width for a dynamic strobe signal based on a predetermined condition, the first pulse width configured to limit a peak current of the dynamic strobe signal below a predetermined threshold during a sense operation; means for sensing a state of the memory cells by applying, at a first time, the dynamic strobe signal with the first pulse width to a plurality of sense modules connected to a plurality of bit lines spanning the array; means for applying a second programming pulse to the array of memory cells; means for determining a second pulse width for the dynamic strobe signal, wherein the second pulse width is smaller than the first pulse width; and means for sensing a state of the memory cells by applying, at a second time, the dynamic strobe signal with the second pulse width to the plurality of sense modules.