# US 2018/0322925 A1 · Memory device and operating method including a partial program operation and a partial erase operation thereof

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- Number: US 2018/0322925 A1
- Document ID: US20180322925A1
- Status: Published application
- Kind: A1
- Application number: 16/031,147
- Filed: 2018-07-10
- Published: 2018-11-08
- Earliest claimed: 2016-04-11
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hee Youl LEE; Ji Ho PARK
- Web page: https://patentgrep.com/patent/US20180322925A1

## CPC

- G11C 16/10: Programming or data input circuits
- G06F 3/0614: {Improving the reliability of storage systems}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/16: for erasing blocks, e.g. arrays, words, groups
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

There are provided a memory device and an operating method thereof. A memory device may include a memory block, peripheral circuits, and a control logic. The memory block may include a plurality of pages arranged in a vertical direction on a substrate. The peripheral circuits may perform a program operation on a selected page. The control logic may control the peripheral circuits to perform a first partial program operation of sequentially programming some of the pages up to a first page. The control logic may perform a first partial erase operation of erasing the other non-programmed pages. The control logic may perform a second partial program operation of partially programming the pages on which the first partial erase operation has been performed.

## Claims

### Claim 1

A method of operating a memory device including a string coupled between a source line and a bit line, the method comprising:
programming a first memory cell from the source line;
programming a first memory cell from the bit line after the first memory cell from the source line is programmed;
programming a second memory cell from the source line after the first memory cell from the bit line is programmed;
programming a second memory cell from the bit line after the second memory cell from the source line is programmed;
programming an Nth memory cell from the source line after the second memory cell from the bit line is programmed;
programming an Nth memory cell from the bit line after the Nth memory cell from the source line is programmed;
erasing memory cells coupled between the Nth memory cell from the source line and the Nth memory cell from the bit line; and
programming the erased memory cells.

### Claim 2

A method of operating a memory device including a string including a source selection transistor, a drain selection transistor and memory cells coupled between the source selection transistor and the drain selection transistor, the method comprising:
programming a first memory cell from the source selection transistor;
programming a first memory cell from the drain selection transistor after the first memory cell from the source selection transistor is programmed;
programming a second memory cell from the source selection transistor after the first memory cell from the drain selection transistor is programmed;
programming a second memory cell from the drain selection transistor after the second memory cell from the source selection transistor is programmed;
programming an Nth memory cell from the source selection transistor after the second memory cell from the drain selection transistor is programmed;
programming an Nth memory cell from the drain selection transistor after the Nth memory cell from the source selection transistor is programmed;
erasing memory cells coupled between the Nth memory cell from the source selection transistor and the Nth memory cell from the drain selection transistor; and
programming the erased memory cells.