# US 2018/0322924 A1 · Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2018/0322924 A1
- Document ID: US20180322924A1
- Status: Published application
- Kind: A1
- Application number: 16/037,898
- Filed: 2018-07-17
- Published: 2018-11-08
- Earliest claimed: 2009-01-30
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Takatoshi MINAMOTO; Toshiki HISADA; Dai NAKAMURA
- Web page: https://patentgrep.com/patent/US20180322924A1

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/24: Bit-line control circuits
- H10B 41/10: characterised by the top-view layout
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 43/35: with cell select transistors, e.g. NAND
- H10W 20/43: Layouts of interconnections
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell unit in which an (N+1) number of memory cells (N is a natural number not less than 1), including charge accumulation layers and control gates formed on the charge accumulation layers, are connected in series;
an (N+1) number of word lines connected to the control gates of 0-th to N-th memory cells connected in series in a one-to-one correspondence;
a driver circuit which supplies a voltage to the memory cells; and
an (N+1) number of first transistors which are formed on (N+1) number of element regions provided in a semiconductor substrate, include gate electrodes formed above the element regions with gate insulating films interposed therebetween, and transfer the voltage to the word lines respectively, each of the first transistors including two impurity diffused layers which are formed at the surface of one of the element regions and one of which is connected to the driver circuit and the other of which is connected to one of the word lines,
wherein the (N+1) number of element regions are electrically separated from one another and the gate electrodes are connected in common, and
above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.