# US 2018/0322922 A1 · Methods and apparatus for pattern matching

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- Number: US 2018/0322922 A1
- Document ID: US20180322922A1
- Status: Published application
- Kind: A1
- Application number: 16/019,650
- Filed: 2018-06-27
- Published: 2018-11-08
- Earliest claimed: 2015-01-12
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Luca De Santis; Tommaso Vali; Kenneth J. Eldredge; Vishal Sarin
- Web page: https://patentgrep.com/patent/US20180322922A1

## CPC

- G11C 15/046: {using non-volatile storage elements}
- G11C 13/06: using magneto-optical elements {(G11C13/042 takes precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/10: Programming or data input circuits
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

## Claims

### Claim 1

A method of pattern matching, comprising:
receiving a pattern to be searched in a memory, the memory comprising a plurality of sets of memory elements, wherein each set of memory elements of the plurality of sets of memory elements is coupled to a separate data line, wherein each set of memory elements of the plurality of sets of memory elements corresponds to a same set of bit positions of the pattern, and wherein each set of memory elements is programmed to contain the same data; and
checking for the pattern to be searched in the memory.

### Claim 2 (depends on 1)

The method of claim 1, wherein a match condition is met when a majority of the data lines coupled to the plurality of sets of memory elements indicates a match for the pattern to be searched.

### Claim 3 (depends on 1)

The method of claim 1, wherein the plurality of sets of memory elements comprises at least three sets of memory elements.

### Claim 4 (depends on 1)

The method of claim 1, wherein the plurality of sets of memory elements comprises N sets of memory elements, and a matching condition is met when at least K sets of memory elements of the N sets of memory elements match, wherein K is greater than N/2.

### Claim 5 (depends on 1)

The method of claim 1, wherein a particular memory element of the plurality of sets of memory elements comprises one or more cell pairs.

### Claim 6 (depends on 5)

The method of claim 5, wherein the particular memory element comprises two or more cell pairs coupled in series in a same string of memory cells.

### Claim 7 (depends on 5)

The method of claim 5, wherein the particular memory element comprises two or more cell pairs aligned in parallel along its respective data line.

### Claim 8

A memory, comprising:
an array of memory cells comprising a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory; and
control circuitry configured to apply a same pair of voltages to control gates of each cell pair of the plurality of cell pairs when checking for a match of the stored bit of data of the plurality of cell pairs and a data value of the particular bit position of the pattern, wherein voltage levels of the same pair of voltages are responsive to the data value of the particular bit position of the pattern.

### Claim 9 (depends on 8)

The memory device of claim 8, wherein the control circuitry is further configured to determine that a match condition is met when each cell pair of the plurality of cell pairs is conducting in response to the pair of voltages applied to their control gates.

### Claim 10 (depends on 8)

The memory device of claim 8, wherein the control circuitry is further configured to determine that a match condition is met when any cell pair of the plurality of cell pairs is conducting in response to the pair of voltages applied to its control gates.

### Claim 11 (depends on 8)

The memory device of claim 8, wherein the plurality of cell pairs comprises two cell pairs.

### Claim 12 (depends on 8)

The memory device of claim 8, wherein the plurality of cell pairs are aligned in at least one manner selected from the group consisting of coupled in series in a same string of memory cells, and aligned in parallel along a same data line.

### Claim 13 (depends on 8)

The memory device of claim 8, wherein the plurality of cell pairs comprises cell pairs coupled in series in a same string of memory cells.

### Claim 14 (depends on 13)

The memory device of claim 13, wherein the plurality of cell pairs further comprises additional cell pairs coupled in series in a different string of memory cells.

### Claim 15 (depends on 13)

The memory device of claim 13, wherein a first cell pair of the plurality of cell pairs programmed to store the bit of data corresponding to the particular bit position is coupled in series with a second cell pair of the plurality of cell pairs programmed to store the bit of data corresponding to the particular bit position, and is coupled in parallel with a third cell pair of the plurality of cell pairs programmed to store the bit of data corresponding to the particular bit position.

### Claim 16 (depends on 13)

The memory device of claim 13, wherein the plurality of cell pairs comprises a first cell pair in a first string of memory cells coupled to a first data line, a second cell pair in the first string of memory cells coupled to the first data line, a third cell pair in a second string of memory cells coupled to a second data line, and a fourth cell pair in the second string of memory cells coupled to the second data line.

### Claim 17

A method of operating a memory, comprising:
receiving a pattern of data to be programmed into a memory array of the memory;
programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of the memory array, and programing a second data state into an other memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern.

### Claim 18 (depends on 17)

The method of claim 17, wherein programming the first data state into the one memory cell of each cell pair of the plurality of cell pairs, and programing the second data state into the other memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern comprises programming the one memory cell and the other memory cell of each cell pair of the plurality of cell pairs to have different threshold voltages.

### Claim 19 (depends on 17)

The method of claim 17, wherein each cell pair of the plurality of cell pairs are coupled in series in a same string of memory cells of the memory array.

### Claim 20 (depends on 17)

The method of claim 17, wherein each cell pair of the plurality of cell pairs are aligned in parallel along a same data line of the memory array.