# US 2018/0322912 A1 · Non-volatile transistor element including a buried ferroelectric material based storage mechanism > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322912 A1 - Document ID: US20180322912A1 - Status: Published application - Kind: A1 - Application number: 15/585,709 - Filed: 2017-05-03 - Published: 2018-11-08 - Earliest claimed: 2017-05-03 - Assignees: Globalfoundries Inc. - Applicants: GLOBALFOUNDRIES Inc. - Inventors: Stefan Duenkel; Ralf Illgen; Ralf Richter; Soeren Jansen - Web page: https://patentgrep.com/patent/US20180322912A1 ## CPC - G11C 11/225: {Auxiliary circuits} - G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells} - G11C 11/223: {using MOS with ferroelectric gate insulating film} - G11C 11/2275: {Writing or programming circuits or methods} - G11C 11/5657: {using ferroelectric storage elements} - G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)} - G11C 16/06: Auxiliary circuits, e.g. for writing into memory - G11C 16/10: Programming or data input circuits - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs} - H10D 30/711: {having floating bodies} - H10D 64/033: {comprising ferroelectric layers} - H10D 64/037: {comprising charge-trapping insulators} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present disclosure provides storage elements, such as storage transistors, wherein at least one storage mechanism is provided on the basis of a ferroelectric material formed in the buried insulating layer of an SOI transistor architecture. In further illustrative embodiments, one further storage mechanism is implemented in the gate electrode structure, thereby providing increased overall information density. In some illustrative embodiments, the storage mechanism in the gate electrode structure is provided in the form of a ferroelectric material. ## Claims ### Claim 1 A non-volatile storage element, comprising: a channel region formed in a semiconductor material; a control electrode structure positioned to control a current flow through said channel region; a first storage mechanism positioned to adjust a value of a threshold voltage of said channel region; and a second storage mechanism positioned to adjust said value of said threshold voltage, said second storage mechanism comprising a ferroelectric material and being configured to enable, in combination with said first storage mechanism, selection of more than two distinct values of said threshold voltage of said channel region. ### Claim 2 (depends on 1) The non-volatile storage element of claim 1, wherein said first storage mechanism and said ferroelectric material of said second storage mechanism are positioned so as to sandwich said channel region in a direction that is substantially perpendicular with respect to a current flow direction of said channel region. ### Claim 3 (depends on 1) The non-volatile storage element of claim 1, wherein said ferroelectric material of said second storage mechanism is provided in a buried insulating layer formed in contact with said channel region. ### Claim 4 (depends on 1) The non-volatile storage element of claim 1, wherein said first storage mechanism comprises a further ferroelectric material. ### Claim 5 (depends on 1) The non-volatile storage element of claim 1, wherein said first storage mechanism comprises a charge trapping layer. ### Claim 6 (depends on 1) The non-volatile storage element of claim 1, wherein said ferroelectric material of said second storage mechanism is formed in said control electrode structure. ### Claim 7 (depends on 1) The non-volatile storage element of claim 1, wherein said first storage mechanism has a first efficiency for adjusting the value of said threshold voltage and said second storage mechanism has a second efficiency for adjusting the value of said threshold voltage and wherein said first efficiency differs from said second efficiency. ### Claim 8 (depends on 1) The non-volatile storage element of claim 1, wherein said first storage mechanism is implemented in said control electrode structure. ### Claim 9 (depends on 1) The non-volatile storage element of claim 1, further comprising a drain region and a source region connected to said channel region so as to form a transistor configuration formed on the basis of a buried insulating layer. ### Claim 10 A non-volatile storage transistor element, comprising: a channel region; a gate electrode structure positioned to control current flow in said channel region; and a buried insulating layer formed below said channel region, said buried insulating layer comprising a ferroelectric material so as to provide a storage mechanism for storing information in a non-volatile manner. ### Claim 11 (depends on 10) The non-volatile storage transistor element of claim 10, wherein said gate electrode structure comprises a further storage mechanism that, in combination with said storage mechanism, provides more than two non-volatile logic states. ### Claim 12 (depends on 10) The non-volatile storage transistor element of claim 10, wherein said gate electrode structure comprises a ferroelectric material as a component of said further storage mechanism. ### Claim 13 (depends on 10) The non-volatile storage transistor element of claim 10, wherein said gate electrode structure comprises at least one of a ferroelectric material and a charge trapping material as a component of said further storage mechanism. ### Claim 14 (depends on 11) The non-volatile storage transistor element of claim 11, wherein said storage mechanism has a first efficiency for adjusting a value of a threshold voltage of said channel region and said further storage mechanism has a second efficiency for adjusting the value of said threshold voltage and wherein said first efficiency differs from said second efficiency. ### Claim 15 (depends on 10) The non-volatile storage transistor element of claim 10, further comprising an electrode material formed below said buried insulating layer for applying an electric field in said ferroelectric material. ### Claim 16 A method, comprising: selecting a first polarization state of a ferroelectric material formed near a channel region of a transistor element; selecting a first storage state of at least one of a charge trapping material and a second ferroelectric material formed near said channel region; assigning a first logic state to a first channel condition induced by said first polarization state and said first storage state; selecting a second storage state of said at least one of a charge trapping material and a second ferroelectric material; assigning a second logic state to a second channel condition induced by said first polarization state and said second storage state; and assigning at least one further logic state to one of said first and second storage states when combined with a second polarization state of said ferroelectric material, said first and second polarization states being inverse to each other. ### Claim 17 (depends on 16) The method of claim 16, wherein said first and second storage states correspond, respectively, to first and second polarization states of said second ferroelectric material. ### Claim 18 (depends on 16) The method of claim 16, wherein said first and second storage states correspond, respectively, to first and second charge trapping states of said charge trapping material. ### Claim 19 (depends on 16) The method of claim 16, wherein said channel condition is determined by a value of a threshold voltage of said channel region. ### Claim 20 (depends on 19) The method of claim 19, wherein logic states are assigned to at least four different values of said threshold voltage.