# US 2018/0322835 A1 · Display device and driving method

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- Number: US 2018/0322835 A1
- Document ID: US20180322835A1
- Status: Published application
- Kind: A1
- Application number: 16/039,515
- Filed: 2018-07-19
- Published: 2018-11-08
- Earliest claimed: 2010-02-12
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Shunpei YAMAZAKI; Jun KOYAMA
- Web page: https://patentgrep.com/patent/US20180322835A1

## CPC

- G09G 3/3614: {Control of polarity reversal in general}
- G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)}
- G09G 3/3655: {Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors}
- G09G 3/3677: {suitable for active matrices only}
- G09G 3/3688: {suitable for active matrices only}
- G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
- G09G 2310/06: Details of flat display driving waveforms
- G09G 2310/08: Details of timing specific for flat panels, other than clock recovery
- G09G 2320/0214: with crosstalk due to leakage current of pixel switch in active matrix panels
- G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
- G09G 2330/021: Power management, e.g. power saving
- G09G 2330/023: using energy recovery or conservation
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

An object is to reduce power consumption of a display device and to suppress deterioration of display quality. As a transistor provided for each pixel, a transistor including an oxide semiconductor layer is used. Note that off-state current of the transistor can be decreased when the oxide semiconductor layer is highly purified. Therefore, variation in the value of a data signal due to the off-state current of the transistor can be suppressed. That is, display deterioration (change) which occurs when writing frequency of the data signal to the pixel including the transistor is reduced (when a break period is lengthened) can be suppressed. In addition, flickers in display which generates when the frequency of an alternating-current driving signal supplied to a signal line in the break period is reduced can be suppressed.

## Claims

### Claim 1

(canceled)

### Claim 2

A display device comprising:
a pixel comprising a first transistor and a display element;
a controller comprising a first circuit, a second circuit, a third circuit, a fourth circuit, a first switch, and a second switch; and
a signal line driver circuit,
wherein the first transistor comprises an oxide semiconductor in a channel formation region,
wherein the oxide semiconductor comprises indium and zinc,
wherein one of a source and a drain of the first transistor is electrically connected to the signal line driver circuit,
wherein the first circuit is configured to generate a data signal,
wherein the second circuit is configured to generate a driving signal having a lower frequency than the data signal,
wherein the third circuit is configured to generate a first clock signal,
wherein the fourth circuit is configured to divide the first clock signal to generate a second clock signal,
wherein the first switch is configured to select the data signal or the driving signal to be output to the signal line driver circuit,
wherein the second switch is configured to select the first clock signal when the first switch selects the data signal, and
wherein the second switch is configured to select the second clock signal when the first switch selects the driving signal.

### Claim 3 (depends on 2)

The display device according to claim 2, wherein an off-state current of the first transistor per unit channel width is smaller than or equal to 1×10−18 A/μm.

### Claim 4 (depends on 2)

The display device according to claim 2, wherein a first off-state current of the first transistor comprising the oxide semiconductor is smaller than a second off-state current of a second transistor comprising an amorphous silicon.

### Claim 5 (depends on 2)

The display device according to claim 2, wherein the controller is configured to output the data signal or the driving signal to the signal line driver circuit selectively.

### Claim 6 (depends on 2)

The display device according to claim 2, wherein a frequency of the first clock signal is the same as a frequency of the data signal.

### Claim 7 (depends on 2)

The display device according to claim 2, wherein a frequency of the second clock signal is the same as a frequency of the driving signal.

### Claim 8 (depends on 2)

The display device according to claim 2, wherein variation in voltage of the driving signal is within a voltage variation range of the data signal.

### Claim 9 (depends on 2)

The display device according to claim 2, wherein the driving signal is an alternating-current driving signal.

### Claim 10 (depends on 2)

The display device according to claim 2, wherein the display element is a liquid crystal element.

### Claim 11

A display device comprising:
a pixel comprising a first transistor and a display element;
a controller comprising a first circuit, a second circuit, a third circuit, a fourth circuit, a first switch, and a second switch;
a signal line driver circuit; and
a scan line driver circuit,
wherein the first transistor comprises an oxide semiconductor in a channel formation region,
wherein the oxide semiconductor comprises indium and zinc,
wherein a gate of the first transistor is electrically connected to the scan line driver circuit,
wherein one of a source and a drain of the first transistor is electrically connected to the signal line driver circuit,
wherein the first circuit is configured to generate a data signal,
wherein the second circuit is configured to generate a driving signal having a lower frequency than the data signal,
wherein the third circuit is configured to generate a first clock signal,
wherein the fourth circuit is configured to divide the first clock signal to generate a second clock signal,
wherein the first switch is configured to select the data signal or the driving signal to be output to the signal line driver circuit,
wherein the second switch is configured to select the first clock signal when the first switch selects the data signal, and
wherein the second switch is configured to select the second clock signal when the first switch selects the driving signal.

### Claim 12 (depends on 11)

The display device according to claim 11, wherein an off-state current of the first transistor per unit channel width is smaller than or equal to 1×10−18 A/μm.

### Claim 13 (depends on 11)

The display device according to claim 11, wherein a first off-state current of the first transistor comprising the oxide semiconductor is smaller than a second off-state current of a second transistor comprising an amorphous silicon.

### Claim 14 (depends on 11)

The display device according to claim 11, wherein the controller is configured to output the data signal or the driving signal to the signal line driver circuit selectively.

### Claim 15 (depends on 11)

The display device according to claim 11, wherein a frequency of the first clock signal is the same as a frequency of the data signal.

### Claim 16 (depends on 11)

The display device according to claim 11, wherein a frequency of the second clock signal is the same as a frequency of the driving signal.

### Claim 17 (depends on 11)

The display device according to claim 11, wherein variation in voltage of the driving signal is within a voltage variation range of the data signal.

### Claim 18 (depends on 11)

The display device according to claim 11, wherein the driving signal is an alternating-current driving signal.

### Claim 19 (depends on 11)

The display device according to claim 11, wherein the display element is a liquid crystal element.