# US 2018/0322684 A1 · Allocation of tiles to processing engines in a graphics processing system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322684 A1 - Document ID: US20180322684A1 - Status: Published application - Kind: A1 - Application number: 16/038,564 - Filed: 2018-07-18 - Published: 2018-11-08 - Earliest claimed: 2015-12-21 - Assignees: Imagination Technologies Limited - Applicants: Imagination Technologies Limited - Inventors: Jonathan Redshaw; Yoong Chert Foo - Web page: https://patentgrep.com/patent/US20180322684A1 ## CPC - G06T 15/005: {General purpose rendering architectures} - G06F 9/505: {considering the load} - G06F 9/5083: {Techniques for rebalancing the load in a distributed system} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G06T 1/60: Memory management - G06T 11/40: Filling planar surfaces by adding surface attributes, e.g. adding colours or textures - G06T 15/04: Texture mapping - G06T 15/40: Hidden part removal - G06T 15/80: Shading - G06T 17/10: Constructive solid geometry [CSG] using solid primitives, e.g. cylinders, cubes - G06T 17/20: Finite element generation, e.g. wire-frame surface description, {tesselation} - H04L 43/16: Threshold monitoring - H04L 67/568: Storing data temporarily at an intermediate stage, e.g. caching - G09G 2360/121: using a cache memory - G09G 2360/122: Tiling - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. The graphics processing system also comprises a cache system for storing graphics data for primitive fragments, the cache system including multiple cache subsystems. Each of the cache subsystems is coupled to a respective set of one or more processing engines. The graphics processing system also comprises a tile allocation unit which operates in one or more allocation modes to allocate tiles to processing engines. The allocation mode(s) include a spatial allocation mode in which groups of spatially adjacent tiles are allocated to the processing engines according to a spatial allocation scheme, which ensures that each of the groups of spatially adjacent tiles is allocated to a set of processing engines which are coupled to the same cache subsystem. ## Claims ### Claim 1 A graphics processing system configured to process primitive fragments using a rendering space which is sub-divided into a plurality of tiles, the system comprising: a plurality of processing engines; and a tile allocation unit configured to operate in a plurality of allocation modes to allocate tiles to the processing engines, wherein the plurality of allocation modes includes a spatial allocation mode and a load balancing allocation mode; wherein the tile allocation unit is configured to maintain, for each of the processing engines, a queue of allocated tiles which are allocated for processing by that processing engine, and wherein the tile allocation unit is configured to monitor the state of the queues to determine an allocation mode in which tiles are to be allocated to the processing engines. ### Claim 2 (depends on 1) The graphics processing system of claim 1, wherein the processing engines are configured to apply one or both of texturing and shading to primitive fragments. ### Claim 3 (depends on 1) The graphics processing system of claim 1, wherein there is a maximum to the number of tiles which can be allocated to a processing engine at any given time. ### Claim 4 (depends on 1) The graphics processing system of claim 1, wherein the tile allocation unit is configured to use two thresholds to the number of tiles in the queues to control the allocation mode in which the tile allocation unit operates, wherein the two thresholds are an allocation threshold and a loading threshold. ### Claim 5 (depends on 4) The graphics processing system of claim 4, wherein the allocation threshold is greater than the loading threshold. ### Claim 6 (depends on 4) The graphics processing system of claim 4, wherein said allocation threshold and said loading threshold are fixed, and wherein a maximum to the number of tiles which can be allocated to a processing engine at any given time is fixed. ### Claim 7 (depends on 4) The graphics processing system of claim 4, wherein there is a maximum to the number of tiles which can be allocated to a processing engine at any given time, and wherein at least one of said maximum to the number of tiles, said allocation threshold and said loading threshold is variable. ### Claim 8 (depends on 4) The graphics processing system of claim 4, wherein the tile allocation unit is configured to, responsive to detecting that the number of allocated tiles in each of the queues is not greater than the allocation threshold, implement an allocation process in the spatial allocation mode to thereby allocate a block of tiles to the processing engines, thereby allocating to each of said plurality of processing engines, a respective one or more tiles from the block of tiles. ### Claim 9 (depends on 4) The graphics processing system of claim 4, wherein the tile allocation unit is configured to, responsive to detecting that the number of allocated tiles in any of the queues is below the loading threshold, allocate tiles to the processing engines in the load balancing allocation mode. ### Claim 10 (depends on 9) The graphics processing system of claim 9, wherein the tile allocation unit is configured to, responsive to detecting that the number of allocated tiles in any of the queues is below the loading threshold: allocate sufficient tiles to the processing engines in the load balancing allocation mode to fill each of the queues; identify the maximum number of tiles currently in any of the queues, and allocate tiles to processing engines such that all of the queues have the identified number of tiles; allocate tiles to processing engines in the load balancing allocation mode such that all of the queues have at least a number of tiles equal to the allocation threshold; or allocate tiles to processing engines in the load balancing allocation mode such that all of the queues have at least a number of tiles equal to the loading threshold. ### Claim 11 (depends on 9) The graphics processing system of claim 9, wherein the tile allocation unit is configured to allocate a block of tiles to the processing engines in one allocation process in the load balancing allocation mode. ### Claim 12 (depends on 1) The graphics processing system of claim 1, wherein, in the load balancing allocation mode, tiles are allocated to the processing engines based on computational loads of the processing engines. ### Claim 13 (depends on 1) The graphics processing system of claim 1, wherein the tile allocation unit is configured, when operating in the load balancing allocation mode, to determine when the loads have been rebalanced, and responsive thereto switch to the spatial allocation mode. ### Claim 14 (depends on 1) The graphics processing system of claim 1, further comprising a cache system configured to store graphics data for use in processing the primitive fragments, the cache system including a plurality of cache subsystems, wherein each of said plurality of cache subsystems is coupled to a respective set of one or more of the processing engines. ### Claim 15 (depends on 14) The graphics processing system of claim 14, wherein, in the spatial allocation mode, groups of spatially adjacent tiles are allocated to the processing engines according to a spatial allocation scheme, said spatial allocation scheme ensuring that each of said groups of spatially adjacent tiles is allocated to a set of processing engines which are coupled to the same cache subsystem. ### Claim 16 (depends on 1) The graphics processing system of claim 1, wherein the graphics processing system is configured to render an image, and wherein the processing engines are configured to output processed primitive fragments for use in generating pixel data representing the rendered image. ### Claim 17 (depends on 1) The graphics processing system of claim 1, further comprising a hidden surface removal unit configured to perform hidden surface removal on the primitive fragments, wherein the hidden surface removal unit comprises a plurality of hidden surface removal modules and a Hidden Surface Removal (HSR) tile allocation unit configured to allocate tiles to the hidden surface removal modules. ### Claim 18 A method of processing primitive fragments in a graphics processing system using a rendering space which is sub-divided into a plurality of tiles, the method comprising: processing primitive fragments at a plurality of processing engines; allocating, in a plurality of allocation modes, tiles to the processing engines, wherein the plurality of allocation modes includes a spatial allocation mode and a load balancing allocation mode; maintaining, for each of the processing engines, a queue of allocated tiles which are allocated for processing by that processing engine; and monitoring the state of the queues to determine an allocation mode in which tiles are to be allocated to the processing engines. ### Claim 19 (depends on 18) The method of claim 18, wherein there is a maximum to the number of tiles which can be allocated to a processing engine at any given time, and wherein said monitoring the state of the queues to determine an allocation mode in which tiles are to be allocated to the processing engines comprises using two thresholds to the number of tiles in the queues to control the allocation mode in which tiles are to be allocated to the processing engines, wherein the two thresholds are an allocation threshold and a loading threshold, and wherein the allocation threshold is greater than the loading threshold. ### Claim 20 A non-transitory computer readable storage medium having stored thereon a computer readable description of an integrated circuit that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a graphics processing system which is configured to process primitive fragments using a rendering space which is sub-divided into a plurality of tiles, the graphics processing system comprising: a plurality of processing engines; and a tile allocation unit configured to operate in a plurality of allocation modes to allocate tiles to the processing engines, wherein the plurality of allocation modes includes a spatial allocation mode and a load balancing allocation mode; wherein the tile allocation unit is configured to maintain, for each of the processing engines, a queue of allocated tiles which are allocated for processing by that processing engine, and wherein the tile allocation unit is configured to monitor the state of the queues to determine an allocation mode in which tiles are to be allocated to the processing engines.