# US 2018/0322235 A1 · Field-effect transistor placement optimization for improved leaf cell routability > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322235 A1 - Document ID: US20180322235A1 - Status: Published application - Kind: A1 - Application number: 15/586,851 - Filed: 2017-05-04 - Published: 2018-11-08 - Earliest claimed: 2017-05-04 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Iris Maria Leefken; Silke Penth; Michael Stetter; Tobias T. Werner - Web page: https://patentgrep.com/patent/US20180322235A1 ## CPC - G06F 30/373: Design optimisation - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 2111/04: Constraint-based CAD - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor-implemented method for automatically generating a layout of a cell of a semiconductor circuit is provided herein. The processor-implemented method includes reading a netlist of the cell. The netlist includes a description of internal electrical nets connecting electrical components of the cell with each other. The processor-implemented method assigning a weight to an internal net of the internal electrical nets and placing the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit. ## Claims ### Claim at position 1 1-7. (canceled) ### Claim 8 A computer program product for automatically generating a layout of a cell of a semiconductor circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: read, by a processor, a netlist of the cell, the netlist including a description of internal electrical nets connecting electrical components of the cell with each other; assign, by the processor, an exclusive internal weight to at least one internal net of the internal electrical nets; and place, by the processor, the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit. ### Claim 9 (depends on 8) The computer program product of claim 8, wherein the weight corresponds to a probability that electrical components respective to the at least one internal net are placed close to each other. ### Claim 10 (depends on 8) The computer program product of claim 8, wherein the program instructions are executable by the processor to cause the processor to identify at least one external net that forms an electrical connection to circuitry belonging to a part of the semiconductor circuit external to the cell. ### Claim 11 (depends on 8) The computer program product of claim 8, wherein the program instructions are executable by the processor to cause the processor to identify at least one internal net that connects without providing an electrical connection to any part of the semiconductor circuit external to the cell. ### Claim 12 (depends on 8) The computer program product of claim 8, wherein the program instructions are executable by the processor to cause the processor to assign a second weight to at least one external net that is lower than the weight of the at least one internal net. ### Claim 13 (depends on 8) The computer program product of claim 8, wherein the program instructions are executable by the processor to cause the processor to place the electrical components, comprises optimizing a total internal net length of the cell, where a length of the at least one internal net is weighted according to the weight. ### Claim 14 (depends on 8) The computer program product of claim 8, wherein the program instructions are executable by the processor to cause the processor to minimize a gate-to-gate net length of the cell. ### Claim 15 A system, comprising a processor and a memory storing program instructions for automatically generating a layout of a cell of a semiconductor circuit thereon, the program instructions executable by the processor to cause the system to: read, by a processor, a netlist of the cell, the netlist including a description of internal electrical nets connecting electrical components of the cell with each other; assign, by the processor, an exclusive internal weight to at least one internal net of the internal electrical nets; and place, by the processor, the electrical components in an area of the semiconductor circuit based on the netlist and the weight to generate the layout of the cell of the semiconductor circuit. ### Claim 16 (depends on 15) The system of claim 15, wherein the weight corresponds to a probability that electrical components respective to the at least one internal net are placed close to each other. ### Claim 17 (depends on 15) The system of claim 15, the program instructions are executable by the processor to cause the system to identify at least one external net that forms an electrical connection to circuitry belonging to a part of the semiconductor circuit external to the cell. ### Claim 18 (depends on 15) The system of claim 15, the program instructions are executable by the processor to cause the system to identify at least one internal net that connects without providing an electrical connection to any part of the semiconductor circuit external to the cell. ### Claim 19 (depends on 15) The system of claim 15, the program instructions are executable by the processor to cause the system to assign a second weight to at least one external net that is lower than the weight of the at least one internal net. ### Claim 20 (depends on 15) The system of claim 15, the program instructions are executable by the processor to cause the system to place the electrical components, comprises optimizing a total internal net length of the cell, where a length of the at least one internal net is weighted according to the weight.