# US 2018/0322234 A1 · Prediction of process-sensitive geometries with machine learning

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- Number: US 2018/0322234 A1
- Document ID: US20180322234A1
- Status: Published application
- Kind: A1
- Application number: 15/588,984
- Filed: 2017-05-08
- Published: 2018-11-08
- Earliest claimed: 2017-05-08
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Liang Cao; Jie Zhang; David N. Power; Eric S. Parent
- Web page: https://patentgrep.com/patent/US20180322234A1

## CPC

- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

Methods according to the disclosure include: predicting process-sensitive geometries (PSGs) in a proposed IC layout based on violations of a set of processing constraints for the proposed IC layout, the set of processing constraints being calculated with a predictive model based on a training data repository having a plurality of optical rule check (ORC) simulations for different IC layouts; identifying actual PSGs in a circuit manufactured using the proposed IC layout; determining whether the predicted PSGs correspond to the actual PSGs in the manufactured circuit as being correct; in response to the predicting being incorrect: adjusting the predictive model based on the actual PSGs, wherein the adjusting includes submitting additional ORC data to the training data repository; and flagging the proposed IC layout as incorrectly predicted; and in response to the predicting being correct, flagging the proposed IC layout as correctly predicted.

## Claims

### Claim 1

A method comprising:
predicting process-sensitive geometries (PSGs) in a proposed IC layout based on violations of a set of processing constraints for the proposed IC layout, the set of processing constraints being calculated with a predictive model based on a training data repository having a plurality of optical rule check (ORC) simulations for different IC layouts;
identifying actual PSGs in a circuit manufactured using the proposed IC layout;
determining whether the predicted PSGs correspond to the actual PSGs in the manufactured circuit as being correct;
in response to the predicting being incorrect:
adjusting the predictive model based on the actual PSGs, wherein the adjusting includes submitting additional ORC data to the training data repository; and
flagging the proposed IC layout as incorrectly predicted; and
in response to the predicting being correct, flagging the proposed IC layout as correctly predicted.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
selecting a set of related ORC data for the proposed IC layout based on the manufactured circuit; and
in response to the proposed IC layout or the related ORC data not being represented in the training data repository, storing the proposed IC layout or the related ORC data in the training data repository.

### Claim 3 (depends on 1)

The method of claim 1, wherein the calculated processing constraints include a minimum pattern width, a minimum pattern separation, a pattern density, and an inter-layer size in the proposed IC layout.

### Claim 4 (depends on 1)

The method of claim 1, wherein the predictive model comprises an artificial neural network (ANN).

### Claim 5 (depends on 1)

The method of claim 1, further comprising adjusting a mask shape for the proposed IC layout based on the actual PSGs.

### Claim 6 (depends on 5)

The method of claim 5, further comprising repeating the predicting, manufacturing, and determining for the proposed IC layout with the adjusted mask shape.

### Claim 7 (depends on 5)

The method of claim 5, further comprising adding ORC simulation data of the proposed IC layout with the adjusted mask shape to the training data repository.

### Claim 8 (depends on 1)

The method of claim 1, wherein the training data repository includes at least one correctly predicted IC layout and at least one incorrectly predicted IC layout.

### Claim 9

A computer program product stored on a computer readable storage medium, the computer program product comprising program code, which, when being executed by at least one computing device, causes the at least one computing device to:
predict process-sensitive geometries (PSGs) in a proposed IC layout based on violations of a set of processing constraints for the proposed IC layout, the set of processing constraints being calculated with a predictive model based on a training data repository having a plurality of optical rule check (ORC) simulations for different IC layouts;
identify actual PSGs in a circuit manufactured using the proposed IC layout;
determine whether the predicted PSGs correspond to the actual PSGs in the manufactured circuit as being correct;
in response to the predicted PSGs being incorrect:
adjust the predictive model based on the actual PSGs, wherein the adjusting includes submitting additional ORC data to the training data repository; and
flag the proposed IC layout as incorrectly predicted; and
in response to the predicted PSGs being correct, flagging the proposed IC layout as correctly predicted.

### Claim 10 (depends on 9)

The computer program product of claim 9, the computer program product further comprising program code for causing the at least one computing device to:
select a set of related ORC data for the proposed IC layout based on the manufactured circuit; and
in response to the proposed IC layout or the related ORC data not being represented in the training data repository, store the proposed IC layout or the related ORC data in the training data repository.

### Claim 11 (depends on 9)

The computer program product of claim 9, wherein the calculated processing constraints include a minimum pattern width, a minimum pattern separation, a pattern density, and an inter-layer size in the proposed IC layout.

### Claim 12 (depends on 9)

The computer program product of claim 9, the computer program product further comprising program code for causing the at least one computing device to adjust a mask shape for the proposed IC layout based on the actual PSGs.

### Claim 13 (depends on 12)

The computer program product of claim 12, the computer program product further comprising program code for causing the at least one computing device to repeat the predicting, manufacturing, and determining for the proposed IC layout with the adjusted mask shape.

### Claim 14 (depends on 12)

The computer program product of claim 12, the computer program product further comprising program code for causing the at least one computing device to add ORC simulation data of the proposed IC layout with the adjusted mask shape to the training data repository.

### Claim 15 (depends on 9)

The computer program product of claim 9, wherein the training data repository includes at least one correctly predicted IC layout and at least one incorrectly predicted IC layout.

### Claim 16

A system comprising at least one computing device configured to perform a method by performing actions including:
predict process-sensitive geometries (PSGs) in a proposed IC layout based on violations of a set of processing constraints for the proposed IC layout, the set of processing constraints being calculated with a predictive model based on a training data repository having a plurality of optical rule check (ORC) simulations for different IC layouts;
identify actual PSGs in a circuit manufactured using the proposed IC layout;
determine whether the predicted PSGs correspond to the actual PSGs in the manufactured circuit as being correct;
in response to the predicted PSGs being incorrect:
adjust the predictive model based on the actual PSGs, wherein the adjusting includes submitting additional ORC data to the training data repository; and
flag the proposed IC layout as incorrectly predicted; and
in response to the predicted PSGs being correct, flagging the proposed IC layout as correctly predicted.

### Claim 17 (depends on 16)

The system of claim 16, wherein the at least one computing device is further configured to:
select a set of related ORC data for the proposed IC layout based on the manufactured circuit; and
in response to the proposed IC layout or the related ORC data not being represented in the training data repository, store the proposed IC layout or the related ORC data in the training data repository.

### Claim 18 (depends on 16)

The system of claim 16, wherein the at least one computing device is further configured to adjust a mask shape for the proposed IC layout based on the actual PSGs.

### Claim 19 (depends on 18)

The system of claim 18, wherein the at least one computing device is further configured to repeat the predicting, manufacturing, and determining for the proposed IC layout with the adjusted mask shape.

### Claim 20 (depends on 16)

The system of claim 16, wherein the at least one computing device is further configured to add ORC simulation data of the proposed IC layout with the adjusted mask shape to the training data repository.