# US 2018/0322079 A1 · Semiconductor apparatus

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- Number: US 2018/0322079 A1
- Document ID: US20180322079A1
- Status: Published application
- Kind: A1
- Application number: 16/034,201
- Filed: 2018-07-12
- Published: 2018-11-08
- Earliest claimed: 2014-01-07
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Naoki Mitsuishi; Seiji Ikari; Katsumasa Uchiyama
- Web page: https://patentgrep.com/patent/US20180322079A1

## CPC

- G06F 13/32: using combination of interrupt and burst mode transfer
- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 2213/2406: Generation of an interrupt or a group of interrupts after a fixed or calculated time elapses
- G06F 2213/2802: DMA using DMA transfer descriptors
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An object is to obtain output data corresponding to input data by referring to table data by a semiconductor apparatus having a simple configuration. An MCU includes a DTC for transferring data from a source address region to a destination address region based on data transfer information in response to a startup request. The DTC performs an operation on second source address information based on data that has been read from first source address information, performs reading based on a result of the operation, and writes read data based on destination address information.

## Claims

### Claim at position 1

1-14. (canceled)

### Claim 15

A semiconductor device having a data transfer controller, the data transfer controller comprising:
an arithmetic logic unit;
a first source address register;
a second source address register;
a transfer destination address register; and
a transfer count register,
wherein the data transfer controller reads a first data based on a first source address specified by the first source address register and a second data based on a second source address specified by the second source address register, and transfers the second data to a transfer destination address specified by the transfer destination address register,
wherein the arithmetic logic unit calculates the first data,
wherein the second source address or the transfer destination address is calculated using the calculated first data, and
wherein the data transfer controller performs an arithmetic operation on the first data, the second source address and the transfer destination address, and a data transfer operation based on the calculated second source address or the calculated transfer destination address for a set number of times specified by the transfer count register.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15,
wherein the second data is a result of performing at least one of a logical operation and a shift operation according to data size of the first data.

### Claim 17 (depends on 15)

The semiconductor device according to claim 15,
wherein the data controller reads a data transfer information based on a data transfer information address which is specified by an activation request,
wherein the data transfer information includes the first source address, the second source address and the transfer destination address to be stored in the first source address register, the second source address register and the transfer destination address register, respectively.

### Claim 18 (depends on 17)

The semiconductor device according to claim 17,
wherein the data transfer information further includes a mode information,
wherein the data controller further includes a mode register storing the mode information, and
wherein one of the second source address and the transfer destination address is calculated by using the second data according to the mode information.

### Claim 19 (depends on 17)

The semiconductor device according to claim 17,
wherein the data transfer information is updated with the calculated second source address or the calculated transfer destination address.