# US 2018/0322011 A1 · Delay circuitry to hold up power to a mass storage device and method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322011 A1 - Document ID: US20180322011A1 - Status: Published application - Kind: A1 - Application number: 15/971,712 - Filed: 2018-05-04 - Published: 2018-11-08 - Earliest claimed: 2017-05-04 - Assignees: Sanmina Corporation - Applicants: Sanmina Corporation - Inventors: Paul Batcheller; Matthew Bowman; Drew G. Doblar; Franz Michael Schuette - Web page: https://patentgrep.com/patent/US20180322011A1 ## CPC - G06F 11/1415: {at system level} - G06F 1/30: Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) - G06F 11/2015: {Redundant power supplies (power supply failure G06F1/30)} - H02H 7/20: for electronic equipment (for converters H02H7/10; for electric measuring instruments G01R1/36; for DC voltage or current semiconductor regulators G05F1/569; for amplifiers H03F1/52; for electronic switching circuits H03K17/08) - H03K 5/00: Manipulating of pulses not covered by one of the other main groups of this subclass (circuits with regenerative action H03K3/00, H03K4/00; by the use of non-linear magnetic or dielectric devices H03K3/45) - H05K 1/0293: {Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches} - G06F 11/1441: {Resetting or repowering} - G06F 2201/86: Event-based monitoring - G11C 5/141: {Battery and back-up supplies} - G11C 16/22: Safety or protection circuits preventing unauthorised or accidental access to memory cells - H03K 2005/00078: {Fixed delay} - H03K 2005/00195: {using FET's} - H05K 2201/10159: Memory - H05K 2201/10181: Fuse - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media. ## Claims ### Claim 1 A computer device, comprising: an enclosure having one or more host computers powered by a power supply; a plurality of non-volatile memory mass storage devices having a volatile memory cache and a non-volatile memory data carrier; a plurality of interposer boards, the one or more host computers communicatively coupled to the plurality of non-volatile memory mass storage devices by the plurality of interposer boards; where at least one of the host computers in the one or more host devices is configured to exchange data and control signals with selected non-volatile memory devices in the plurality of non-volatile memory mass storage devices; and where each of the interposer boards in the plurality of interposer boards comprises: a first e-fuse to gate power to a logic circuit on the at least one interposer board along a data path to a first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices; a second e-fuse to gate power to the first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices, wherein the first and the second e-fuses are logically connected to fault the second e-fuse when a fault condition occurs on the first e-fuse; and a delay circuit, coupled between the first e-fuse and the second e-fuse, configured to delay the fault of the second e-fuse after the fault of the first e-fuse. ### Claim 2 (depends on 1) The computer device of claim 1, further comprising a midplane coupled between the one or more host devices and the plurality of interposer boards. ### Claim 3 (depends on 1) The computer device of claim 1, wherein the fault of the second e-fuse causes power to be turned Off to the first non-volatile memory mass storage device after a time delay caused by the delay circuit, the time delay relative to the fault of the first e-fuse. ### Claim 4 (depends on 3) The computer device of claim 3, wherein the time delay provides sufficient time for data to be copied from the volatile cache memory in the first non-volatile memory mass storage device to the non-volatile memory data carrier. ### Claim 5 (depends on 1) The computer device of claim 1, further comprising: a multiplexing control logic circuit on the interposer boards, the multiplexing logic configured to select a non-volatile mass storage device in the plurality of non-volatile memory devices by the one or more host computers, where a power converter powers the multiplexing control logic circuit. ### Claim 6 (depends on 5) The computer device of claim 5, wherein the delay circuit comprises: an array of capacitors having one or more capacitors; a supply voltage adapted to charge the one or more capacitors in the array of capacitors; a first metal-oxide-semiconductor field-effect transistor (MOSFTET) connected to the array of capacitors, wherein when in a non-fault condition, the first MOSFET is in a low-resistance state to connect the supply voltage to the one or more capacitors in the array of capacitors to a ground; and when a fault condition from the power converter powering the multiplexing logic circuit and connected to a gate of the first MOSFET switches the first MOSFET to a high resistance state to ground, the high resistance state of the first MOSFET preventing the supply voltage to the array of capacitors from draining to ground and causing charging of the array of capacitors; and a second MOSFET coupled to the array of capacitors, wherein when a charge of the one or more capacitors in the array of capacitors exceeds a gate threshold voltage of the second MOSFET, the second MOSFET switches from a high resistance state to a low resistance state, and the low resistance state of the second MOSFET causes the second e-fuse to turn Off power to the first non-volatile memory mass storage device. ### Claim 7 (depends on 6) The computer device of claim 6, further comprising a first resistor coupled between the supply voltage and the array of capacitors for limiting an inrush current; and wherein a second resistor coupled between the array of capacitors and the first MOSFET for limiting a drain of the first MOSFET to ground. ### Claim 8 (depends on 6) The computer device of claim 6, wherein the second e-fuse includes a sense resistor for sensing an over current condition on the first non-volatile memory mass storage device. ### Claim 9 (depends on 1) The computer device of claim 1, wherein the non-volatile memory mass storage devices include non-volatile memory express (NVMe) devices and/or peripheral component interconnect express (PCIe) devices. ### Claim 10 (depends on 6) The computer device of claim 6, wherein the supply voltage is 12 volts. ### Claim 11 (depends on 6) The computer device of claim 6, wherein the power converter provides a voltage of 3.3 volts or 1.8 volts. ### Claim 12 A method for power fail protection of a plurality of non-volatile memory devices in a computer device having an enclosure, a power supply unit, one or more host computers, a midplane and interposer boards to connect non-volatile memory mass storage devices with the one or more host computers, the method comprising: configuring a host computer to exchange data and control signals with a selected non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices; providing power from a midplane supply voltage source to a multiplexing logic circuit along a data/signal path to the plurality of non-volatile memory mass storage device, and from the midplane supply voltage source to the plurality of non-volatile memory mass storage device; and automatically triggering a power shutoff, after a predictable time delay, of the plurality of non-volatile memory mass storage devices upon detecting a power fault condition along the data/signal path. ### Claim 13 (depends on 12) The method of claim 12, wherein the time delay is effectuated by delay circuit including an array of capacitors, the array of capacitors being charged by the midplane supply voltage source. ### Claim 14 (depends on 12) The method of claim 12, wherein the time delay provides sufficient time for data to be copied from a cache memory in the first non-volatile memory mass storage device to the non-volatile memory data carriers. ### Claim 15 A circuit, comprising: a non-volatile memory mass storage device having a volatile memory device and non-volatile data carrier, the volatile memory device configured to cache data prior to storing the data on non-volatile memory data carriers in the plurality of non-volatile memory mass storage devices; a power supply providing power, along a first power path, to a logic circuit along a data path to the storage device, and along a second power path to the storage device; a power fault detection circuit adapted to remove power from the second power path when a power fault is detected along the first power path; and a delay circuit configured to delay shutting off the non-volatile memory mass storage device after detection of the power fault along the first power path, the delay circuit providing time for the data to be copied from the volatile memory device to the non-volatile memory data carriers. ### Claim 16 (depends on 15) The circuit of claim 15, wherein the delay circuit comprises: an array of capacitors having one or more capacitors; a supply voltage adapted to charge the one or more capacitors in the array of capacitors; a first metal-oxide-semiconductor field-effect transistor (MOSFTET) connected to the array of capacitors, wherein when in a non-fault condition, the first MOSFET is in a low-resistance state to connect the supply voltage to the one or more capacitors in the array of capacitors to a ground; and when a fault condition from the power converter powering the multiplexing logic circuit and connected to a gate of the first MOSFET switches the first MOSFET to a high resistance state to ground, the high resistance state of the first MOSFET preventing the supply voltage to the array of capacitors from draining to the ground and causing charging of the array of capacitors; and a second MOSFET coupled to the array of capacitors, wherein when a charge of the one or more capacitors in the array of capacitors exceeds a gate threshold voltage of the second MOSFET, the second MOSFET switches from a high resistance state to a low resistance state, and the low resistance state of the second MOSFET causes the second e-fuse to turn Off power to the first non-volatile memory mass storage device. ### Claim 17 (depends on 16) The circuit of claim 16, further comprising a first resistor coupled between the supply voltage and the array of capacitors for limiting an inrush current; and wherein a second resistor coupled between the array of capacitors and the first MOSFET for limiting a drain of the first MOSFET to the ground. ### Claim 18 A computer device, comprising: an enclosure having one or more host computers powered by a power supply; a plurality of non-volatile memory mass storage devices; a plurality of interposer boards, the one or more host computers communicatively coupled to the plurality of non-volatile memory mass storage devices by the plurality of interposer boards; a midplane coupled between the one or more host devices and the plurality of interposer boards; where at least one of the host computers in the one or more host devices configured to exchange data and control signals with selected non-volatile memory mass storage devices in the plurality of non-volatile memory mass storage devices; and where each of the interposer boards in the plurality of interposer boards comprises: a first e-fuse to gate power to a logic circuit on the at least one interposer board along a data path to a first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices; a second e-fuse to gate power to the first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices, wherein the first and the second e-fuses are logically connected to fault the second e-fuse when a fault condition occurs on the first e-fuse; and a delay circuit, coupled between the first e-fuse and the second e-fuse, configured to delay the fault of the second e-fuse after the fault of the first e-fuse. ### Claim 19 (depends on 18) The computer device of claim 18, wherein the delay circuit comprises: an array of capacitors having one or more capacitors; a midplane supply voltage source adapted to charge the one or more capacitors in the array of capacitors; a first metal-oxide-semiconductor field-effect transistor (MOSFTET) connected to the array of capacitors, wherein in a non-fault condition, the first MOSFET is in a low-resistance state to connect the midplane supply voltage source to the one or more capacitors in the array of capacitors to a ground and wherein a fault condition from the power converter powering the multiplexing logic circuit and connected to a gate of the first MOSFET switches the first MOSFET to a high resistance state to ground, the high resistance state of the first MOSFET prevents the supply voltage to the array of capacitors from draining to the ground and causing charging of the array of capacitors; and a second MOSFET coupled to the array of capacitors, when a charge of the one or more capacitors in the array of capacitors exceeds a gate threshold voltage of the second MOSFET the second MOSFET switches from a high resistance state to a low resistance state, and the low resistance state of the second MOSFET causes the second e-fuse to turn Off power to the plurality of non-volatile memory mass storage device. ### Claim 20 (depends on 19) The computer device of claim 19, further comprising a first resistor coupled between the midplane supply voltage and the array of capacitors for limiting an inrush current; and a second resistor coupled between the array of capacitors and the first MOSFET for limiting a drain of the first MOSFET to the ground. ### Claim 21 (depends on 19) The computer device of claim 19, wherein the second e-fuse includes a sense resistor for sensing an over current condition on the first non-volatile memory mass storage device.