# US 2018/0322007 A1 · Morphable ecc encoder/decoder for nvdimm over ddr channel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322007 A1 - Document ID: US20180322007A1 - Status: Published application - Kind: A1 - Application number: 15/675,679 - Filed: 2017-08-11 - Published: 2018-11-08 - Earliest claimed: 2017-05-08 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Dimin NIU; Mu-Tien CHANG; Hongzhong ZHENG - Web page: https://patentgrep.com/patent/US20180322007A1 ## CPC - G06F 11/1044: {with specific ECC/EDC distribution} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 13/4239: {with asynchronous protocol} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A hardware coding mechanism is described. The coding mechanism may include a first encoder to produce a first code using a base number of bits and a second encoder to produce a second code using a supplementary number of bits. The second code and the first code together may be stronger than the first code alone. A mode register stored in a storage may specify whether a switch to the second encoder is open or closed: the first coder is always used. ## Claims ### Claim 1 A coding mechanism implemented in hardware, comprising: a first encoder to produce a first code for a data, the first code including a base number of bits; a second encoder to produce a second code for the data, the second code including a supplementary number of bits; storage for a mode register; and a switch responsive to the mode register to control whether or not the second encoder is used, wherein the first encoder is always used to produce the first code and the second encoder is optionally used to produce the second code, and wherein the second code together with the first code provides a stronger encoding than the first code alone. ### Claim 2 (depends on 1) A coding mechanism according to claim 1, wherein the mode register is operative to store a value indicating whether or not the switch is to use the second encoder. ### Claim 3 (depends on 2) A coding mechanism according to claim 2, wherein the mode register is operative to store the value indicating whether or not the switch is to use the second encoder responsive to whether or not the supplementary number of bits is greater than zero. ### Claim 4 (depends on 1) A coding mechanism according to claim 1, wherein the first encoder and the second encoder share a partial hardware implementation. ### Claim 5 A coding mechanism implemented in hardware, comprising: a first decoder to produce a first result for a data and a first code, the first code including a base number of bits; a second decoder to produce a second result for the data and at least a second code, the second code including a supplementary number of bits; storage for a mode register; and a switch responsive to the mode register to control whether or not the second decoder is used, wherein the first decoder is always used to produce the first result and the second decoder is optionally used to produce the second result, and wherein the second result together with the first result provides a stronger decoding than the first result alone. ### Claim 6 (depends on 5) A coding mechanism according to claim 5, wherein the second decoder is operative to produce the second result responsive to the data, the first code, and the second code. ### Claim 7 (depends on 5) A coding mechanism according to claim 5, wherein the mode register is operative to store a value indicating whether or not the switch indicates to use the second decoder. ### Claim 8 (depends on 7) A coding mechanism according to claim 7, wherein the mode register is operative to store the value indicating whether or not the switch is to use the second decoder responsive to whether or not the supplementary number of bits is greater than zero. ### Claim 9 (depends on 5) A coding mechanism according to claim 5, wherein the first decoder and the second decoder share a partial hardware implementation. ### Claim 10 A method, comprising: receiving data for a memory transaction; determining a number of bits available for error management during the memory transaction, wherein the number of bits available for error management include a base number of bits and a supplementary number of bits; performing a first error management coding for the data based on the base number of bits; and performing a second error management coding for the data based on the supplementary number of bits. ### Claim 11 (depends on 10) A method according to claim 10, wherein: performing a first error management coding for the data based on the base number of bits includes performing a first encoding for the data based on the base number of bits; and performing a second error management coding for the data based on the supplementary number of bits includes performing a second encoding for the data based on the supplementary number of bits. ### Claim 12 (depends on 11) A method according to claim 11, wherein: performing a first encoding for the data based on the base number of bits includes producing a first code; and performing a second encoding for the data based on the supplementary number of bits includes producing a second code. ### Claim 13 (depends on 12) A method according to claim 12, wherein the second code together with the first code provides a stronger error management coding than the first code alone. ### Claim 14 (depends on 10) A method according to claim 10, wherein: performing a first error management coding for the data based on the base number of bits includes performing a first decoding for the data based on the base number of bits; and performing a second error management coding for the data based on the supplementary number of bits includes performing a second decoding for the data based on the supplementary number of bits. ### Claim 15 (depends on 14) A method according to claim 14, wherein: performing a first decoding for the data based on the base number of bits includes performing a first decoding responsive to the data and a first code based on the base number of bits; and performing a second decoding for the data based on the supplementary number of bits includes performing a second decoding responsive to the data and at least a second code. ### Claim 16 (depends on 15) A method according to claim 15, wherein performing a second decoding responsive to the data and at least a second code includes performing a second decoding responsive to the data, the first code, and the second code. ### Claim 17 (depends on 10) A method according to claim 10, wherein performing a second error management coding for the data based on the supplementary number of bits includes performing the second error management coding for the data based on the supplementary number of bits only if the supplementary number of bits is greater than zero. ### Claim 18 (depends on 10) A method according to claim 10, wherein: performing a first error management coding for the data based on the base number of bits includes supporting error detection in the data; and performing a second error management coding for the data based on the supplementary number of bits includes supporting error correction in the data. ### Claim 19 (depends on 10) A method according to claim 10, wherein performing a second error management coding for the data based on the supplementary number of bits includes performing the second error management coding for the data based on the supplementary number of bits from at least the second error management coding and a third error management coding. ### Claim 20 (depends on 19) A method according to claim 19, wherein performing the second error management coding for the data based on the supplementary number of bits from at least the second error management coding and a third error management coding includes performing the third error management coding for the data based on a second supplementary number of bits.