# US 2018/0322005 A1 · Device and system including adaptive repair circuit

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- Number: US 2018/0322005 A1
- Document ID: US20180322005A1
- Status: Published application
- Kind: A1
- Application number: 16/032,368
- Filed: 2018-07-11
- Published: 2018-11-08
- Earliest claimed: 2014-06-17
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sang-Hoon SHIN; Hae-Suk LEE; Han-Vit JUNG; Kyo-Min SOHN
- Web page: https://patentgrep.com/patent/US20180322005A1

## CPC

- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/0703: {Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation}
- G06F 11/0796: {Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element}
- G06F 11/142: {Reconfiguring to eliminate the error (group management mechanisms in a peer-to-peer network H04L67/1044)}
- G06F 11/1423: {by reconfiguration of paths}
- G06F 11/1616: {where the redundant component is an I/O device or an adapter therefor}
- G06F 11/18: using passive fault-masking of the redundant circuits {(error detection by comparing the output of redundant processing systems with continued operation after detection of the error G06F11/165)}
- G06F 11/2002: {where interconnections or communication control functionality are redundant (flexible arrangements for bus networks involving redundancy H04L12/40176)}
- G06F 11/2017: {where memory access, memory control or I/O control functionality is redundant (redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A device, system, and/or method includes an internal circuit configured to perform at least one function, an input-output terminal set and a repair circuit. The input-output terminal set includes a plurality of normal input-output terminals connected to an external device via a plurality of normal signal paths and at least one repair input-output terminal selectively connected to the external device via at least one repair signal path. The repair circuit repairs at least one failed signal path included in the normal signal paths based on a mode signal and fail information signal, where the mode signal represents whether to use the repair signal path and the fail information signal represents fail information on the normal signal paths. Using the repair circuit, various systems adopting different repair schemes may be repaired and cost of designing and manufacturing the various systems may be reduced.

## Claims

### Claim 1

A memory system comprising:
a memory controller;
a memory device comprising:
N number of input-output terminals and a repair input-output terminal disposed in an order of first to Nth input-output terminals and the repair input-output terminal, the N being a natural integer; and
an adaptive repair circuit configured to perform a first repair mode in response to a first mode signal and a first fail information, and to perform a second repair mode in response to a second mode signal and a second fail information; and
an interposer including a plurality of signal paths disposed in accordance with the order of the input-output terminals, and each of the plurality of signal paths connecting each of the input-output terminals to a corresponding terminal of the memory controller, wherein,
in the first repair mode, when the first fail information indicates that jth signal path connected to jth input-output terminal has failed, j being a natural integer smaller than N, the adaptive repair circuit is configured to replace each of jth to N−1th signal paths with each of j+1th to Nth signal paths respectively, and
in the second repair mode, when the second fail information indicates that kth signal path connected to kth input-output terminal failed, k being a natural integer equal to or smaller than N, the adaptive repair circuit is configured to replace each of the kth to Nth signal paths with each of k+1th to Nth signal paths and a repair signal path which is connected to the repair input-output terminal respectively.

### Claim 2 (depends on 1)

The memory system of claim 1, wherein
the first to N−1th input-output terminals are main input-output terminals;
the Nth input-output terminal is a sub input-output terminal; and
in the first repair mode, the sub input-output terminal is not electrically connected to any of the plurality of signal paths, and
in the second repair mode, the sub input-output terminal is connected to the repair signal path.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein
the main input-output terminals are configured to transfer main signals for main operation of the memory device;
the main operation is one of a read operation and a write operation; and
the sub input-output terminal is configured to transfer a sub signal for sub operation of the memory device, the sub operation and the sub signal are data bus inversion operation and a data bus inversion signal respectively.

### Claim 4 (depends on 1)

The memory system of claim 1, wherein, in the first repair mode, the first to j−1th input-output terminals are connected to the first to j−1th signal paths respectively, and in the second repair mode, the first to k−1th input-output terminals are connected to the first to k−1th signal paths respectively.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the memory controller is configured to provide the first fail information and the second fail information.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein the memory controller includes a built-in self-test (BIST) circuit configured to generate the first fail information and the second fail information.

### Claim 7 (depends on 6)

The memory system of claim 6, wherein the BIST circuit is configured to test the plurality of signal paths connecting the memory controller and the memory device while rebooting the memory system to provide the first and/or second fail information.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein the memory controller and the memory device are mounted on the interposer.

### Claim 9 (depends on 1)

The memory system of claim 1, wherein the memory system further includes a substrate on which the interposer in mounted.

### Claim 10 (depends on 9)

The memory system of claim 9, wherein the memory system further includes a conductive bump formed on a lower surface of the substrate for connecting the memory system to an external device.

### Claim 11 (depends on 1)

The memory system of claim 1, wherein the memory device comprising:
a master chip; and
a slave chip stacked on the master chip, the slave chip configured to transfer and receive electrical signals to/from the master chip through through-silicon-vias (TSVs), and the slave chip including an internal circuit configured to perform at least one function.

### Claim 12 (depends on 11)

The memory system of claim 11, wherein the adaptive repair circuit is included in the master chip.

### Claim 13 (depends on 1)

The memory system of claim 1, further comprising:
a mode register set configured to set each of the first mode signal and the second mode through a mode register set operation.

### Claim 14

A memory system, comprising:
a first sub system;
a second sub system comprising:
a plurality of input-output terminals disposed in an order of a first group of input-output terminals, a repair input-output terminal, and a second group of input-output terminals, the first group of input-output terminals including N number of input-output terminals disposed in an order of first to Nth input-output terminals and the second group of input-output terminals including M number of input-output terminals disposed in an order of first to Mth input-output terminals, the N and M being natural integers; and
an adaptive repair circuit configured to perform a repair operation in response to a fail information; and
an interposer including a first group of signal paths disposed in accordance with the order of the first group of input-output terminal and each of the first group of signal paths connecting each of the first group of input-output terminals of the second sub system to corresponding terminal of the first sub system, a repair signal path connecting the repair input-output terminals of the second sub system to corresponding terminal of the first sub system, and a second group of signal paths disposed in accordance with the order of the second group of input-output terminals and each of the second group of signal paths connecting each of the second group of input-output terminals of the second sub system to corresponding terminal of the first sub system, wherein,
when the fail information indicates that jth signal path in the first group of signal paths failed, the adaptive repair circuit is configured to replace each of the jth to Nth input-output terminals of the first group of input-output terminals with each of j+1th to Nth signal paths of the first group of signal paths and the repair signal path respectively, and
when the fail information indicates that kth signal path in the second group of signal paths failed, the adaptive repair circuit is configured to replace each of the kth to Mth input-output terminals of the second group of input-output terminals to each of k+1th to Mth signal paths of the second group of signal paths and the repair signal path respectively, j and k are natural integers, and equal to or smaller than N and M respectively.

### Claim 15 (depends on 14)

The memory system of claim 14, wherein the N and the M are the same.

### Claim 16 (depends on 14)

The memory system of claim 14, wherein
when the fail information indicates that jth signal path among the first group of signal path failed, the adaptive repair circuit is further configured to connect each of the first to j−1th input-output terminals of the first group of input-output terminals to each of first to j−1th signal paths of the first group of signal paths respectively; and
when the fail information indicates that kth signal path in the second group of signal paths failed, the adaptive repair circuit is further configured to replace each of the first to k−1th input-output terminals of the second group of input-output terminals to each of first to k−1th signal paths of the second group of signal paths respectively.

### Claim 17 (depends on 16)

The memory system of claim 16, wherein the repair signal path is located between the first group of signal paths and the second group of signal paths.

### Claim 18 (depends on 17)

The memory system of claim 17, wherein the repair signal path is shared by both the Nth input-output terminal of the first group of input-output terminals and the Mth input-output terminal of the second group of input-output terminals.

### Claim 19 (depends on 14)

The memory system of claim 14, wherein the first sub system and the second sub system are a master chip and a slave chip respectively, the slave chip is stacked on the master chip and configured to transfer and receive electrical signals to/from the master chip through through-silicon-vias (TSVs).

### Claim 20 (depends on 19)

The memory system of claim 19, wherein the adaptive repair circuit is included in the master chip.