# US 2018/0322002 A1 · Controller that receives a cyclic redundancy check (crc) code for both read and write data transmitted via bidirectional data link

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- Number: US 2018/0322002 A1
- Document ID: US20180322002A1
- Status: Published application
- Kind: A1
- Application number: 16/022,791
- Filed: 2018-06-29
- Published: 2018-11-08
- Earliest claimed: 2006-01-11
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Yuanlong WANG; Frederick A. WARE
- Web page: https://patentgrep.com/patent/US20180322002A1

## CPC

- G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)}
- G06F 11/076: {by exceeding a count or rate limit, e.g. word- or bit count limit}
- G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)}
- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1402: {Saving, restoring, recovering or retrying}
- G06F 13/4286: {using a handshaking protocol, e.g. RS232C link}
- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M 13/29: combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M 13/2906: {using block codes (H03M13/2957 takes precedence)}
- H03M 13/611: {Specific encoding aspects, e.g. encoding by means of decoding}
- H04L 1/0061: {Error detection codes}
- H04L 1/08: by repeating transmission, e.g. Verdan system {(H04L1/1858 and H04L1/189 take precedence)}
- H04L 1/1867: Arrangements specially adapted for the transmitter end
- G06F 11/1044: {with specific ECC/EDC distribution}
- H04L 1/0003: {by switching between different modulation schemes}
- H04L 1/0008: {by supplementing frame payload, e.g. with padding bits}
- H04L 2001/0093: {Point-to-multipoint}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

## Claims

### Claim 1

A controller, comprising:
a plurality of transmitter circuits to transmit, to a memory device, write data corresponding to a write operation;
a plurality of first receiver circuits to receive, from the memory device, read data corresponding to a read operation;
an encoder circuit to generate first cyclic redundancy check (CRC) check information corresponding to the write data, and to generate second CRC check information corresponding to the read data;
a second receiver circuit to receive first CRC information, generated by the memory device, that corresponds to the write data and to receive second CRC information, generated by the memory device, that corresponds to the read data; and,
a comparison circuit to determine, based on the first CRC check information and the first CRC information, whether a first error occurred, and to determine, based on the second CRC check information and the second CRC information, whether a second error occurred.

### Claim 2 (depends on 1)

The controller of claim 1, wherein the plurality of first receiver circuits operates at a bandwidth that is greater than the second receiver circuit.

### Claim 3 (depends on 1)

The controller of claim 1, further comprising:
an interface to transmit at least a write command and a read command, the write operation to be performed by the memory device in response to the write command and the read operation to be performed by the memory device in response to the read command, the write command and the read command to be transmitted in a first order.

### Claim 4 (depends on 3)

The controller of claim 3, wherein the second receiver circuit is to receive the first CRC information and the second CRC information in the first order.

### Claim 5 (depends on 4)

The controller of claim 4, wherein there is to be a first latency from the transmission of the write command to the reception of the first CRC information and a second latency from the transmission of the read command to the reception of the second CRC information.

### Claim 6 (depends on 1)

The controller of claim 1, wherein the second receiver circuit further comprises at least one synchronization circuit to receive the first CRC information and the second CRC information.

### Claim 7 (depends on 1)

The controller of claim 1, wherein at least a portion of the read data and the second CRC information are to be received concurrently.

### Claim 8

A controller, comprising:
a bidirectional interface to transmit write data to be stored by a DRAM device and to receive read data stored by the DRAM device, the write data to include at least a write group of bits to be stored by the DRAM device and the read data to include at least a read group of bits to be received from the DRAM device;
a cyclic redundancy check (CRC) encoder to receive the write group of bits and the read group of bits, the CRC encoder to output write error check bits corresponding the write group of bits and read error check bits corresponding to the read group of bits;
a unidirectional interface to receive, from the DRAM device, write check bits corresponding to the write group of bits, and to receive, from the DRAM device, read check bits corresponding to the read group of bits; and,
a comparison circuit to determine, based on the write error check bits and the write check bits, whether a first error occurred, and to determine, based on the read error CRC check bits and the read check bits, whether a second error occurred.

### Claim 9 (depends on 8)

The controller of claim 8, wherein the write group of bits and the read group of bits are input to a parity circuit of the CRC encoder in groups of sixteen (16) bits.

### Claim 10 (depends on 8)

The controller of claim 8, wherein the write check bits are to be received relative to the read check bits in an order that corresponds to an order that the write group of bits is transmitted by the bidirectional interface relative to the read group of bits being received by the bidirectional interface.

### Claim 11 (depends on 8)

The controller of claim 8, further comprising:
an interface to transmit at least a write command and a read command, the write group of bits to be received, by the DRAM device, in response to the write command and the read group of bits to be transmitted, by the DRAM device, in response to the read command, the write command and the read command to be transmitted in a first order.

### Claim 12 (depends on 8)

The controller of claim 8, wherein the write check bits and the read check bits are received by the unidirectional interface in the first order.

### Claim 13 (depends on 11)

The controller of claim 11, wherein there is a first latency from the write command to a start of the transmission of the write check bits by the DRAM device and a second latency from the read command to a start of the transmission of the read check bits by the DRAM device.

### Claim 14 (depends on 8)

The controller of claim 8, further comprising:
at least one synchronization circuit to receive the write check bits and the read check bits from the unidirectional interface.

### Claim 15

A controller integrated circuit, comprising:
a first plurality of transmitters to transmit, to a DRAM device via a command/address link, a first command for DRAM device to perform a first read operation, and to transmit a second command for DRAM device to perform a first write operation;
a second plurality of transmitters to transmit, to the DRAM device via a bidirectional link, first write data corresponding to the first write operation;
a first plurality of receiver circuits to receive, from the bidirectional link, first read data corresponding to the first read operation;
an encoder circuit to generate first cyclic redundancy check (CRC) check information corresponding to the first read data, and to generate second CRC check information corresponding to the first write data;
a receiver circuit to receive, first CRC information generated by the DRAM device and second CRC information generated by the DRAM device; and,
a comparison circuit to determine, based on the first CRC check information and the first CRC information, whether a first error occurred, and to determine, based on the second CRC check information and the second CRC information, whether a second error occurred.

### Claim 16 (depends on 15)

The controller integrated circuit of claim 15, wherein the first plurality of transmitters is to transmit a third command to perform, by the DRAM device, a second read operation that is a retry of the first read command, the third command being sent in response to the comparison circuit determining the first error occurred.

### Claim 17 (depends on 16)

The controller integrated circuit of claim 16, wherein the first plurality of transmitter is to transmit a fourth command to perform, by the DRAM device, a second write operation that is a retry of the first write command, the fourth command being sent in response to the comparison circuit determining the second error occurred.

### Claim 18 (depends on 15)

The controller integrated circuit of claim 15, wherein the first plurality of transmitters is to transmit a third command to perform, by the DRAM device, a second write operation that is a retry of the first write command, the third command being sent in response to the comparison circuit determining the second error occurred.

### Claim 19 (depends on 15)

The controller integrated circuit of claim 15, wherein the second command is to be transmitted in immediate succession with the first command and the second CRC information is to be received in immediate succession with the first CRC information.

### Claim 20 (depends on 19)

The controller integrated circuit of claim 19, wherein the first write data is to be transmitted in immediate succession with the reception of the first read data.