# US 2018/0322001 A1 · Methods for operating multicore processors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0322001 A1 - Document ID: US20180322001A1 - Status: Published application - Kind: A1 - Application number: 15/773,774 - Filed: 2016-10-21 - Published: 2018-11-08 - Earliest claimed: 2015-11-12 - Assignees: Siemens Aktiengesellschaft - Applicants: Siemens Aktiengesellschaft - Inventors: Michael Armbruster; Christian Buckl; Ludger Fiege; Andreas Zirkler; Martin Bischoff - Web page: https://patentgrep.com/patent/US20180322001A1 ## CPC - G06F 11/1497: Time redundant execution of software on a single processing unit - G06F 11/0724: {in a multiprocessor or a multi-core unit (multiprocessors per se G06F15/80)} - G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)} - G06F 11/0754: {by exceeding limits} - G06F 11/0739: {in a data processing system embedded in automotive or aircraft systems} - G06F 11/2035: {without idle spare hardware} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The disclosure relates to at least two processor cores of a multicore processor for dual-lane computing of a security-critical application. The two processor cores are used to full capacity in different working cycles for computing operations of different applications, rather than computing operations being redundantly carried out by both processor cores in each computing cycle. This advantageously avoids duplication of the computational capacity required. For the processor cores to monitor each other, the computing operations are alternatingly carried out by the two processor cores. Any errors may be avoided by the error detection mechanisms described. Although the quality of the error detection is somewhat lower than the “dual-lane operation” known from the prior art with parallel, redundant multi-lane calculations, the quality of the error detection may satisfy the requirement of lower computational outlay, (e.g., when an economic implementation of the control system is required). The disclosure therefore combines the requirements of a sufficiently secure error detection with an economic distribution of the computational capacity. ## Claims ### Claim 1 A method for operating a multicore processor on which an application comprising a plurality of cyclical computing operations is executed, wherein a temporally measured working cycle is provided for calculating a respective computing operation, the method comprising: calculating a computing operation on a processor core of the multicore processor which is allocated according to a distribution scheme; determining at least one distance between a current result of the computing operation and at least one result of a computing operation at least one working cycle behind within a current working cycle and based on a comparison scheme; outputting an error indication when at least one distance is outside an expected value; and calculating a subsequent computing operation on a processor core of the multicore processor which is allocated according to the distribution scheme. ### Claim 2 (depends on 1) The method of claim 1, wherein the computing operations are each alternately allocated to one processor core of the multicore processor according to the distribution scheme. ### Claim 3 (depends on 1) The method of claim 1, wherein an allocation to a first processor core of the multicore processor for a predefinable plurality of working cycles is provided according to the distribution scheme before the allocation is changed to a second processor core of the multicore processor. ### Claim 4 (depends on 3) The method of claim 3, wherein, when the error indication is output, the plurality of working cycles for allocation to the first processor core is increased. ### Claim 5 (depends on 2) The method of claim 2, wherein the computing operations are each allocated to one of at least three processor cores of the multicore processor in a rotating manner. ### Claim 6 (depends on 1) The method of claim 1, wherein a first distance is determined from the previous result of the computing operation of the one working cycle behind and the result of the current working cycle according to the comparison scheme. ### Claim 7 (depends on 6) The method of claim 6, wherein the error indication is output when the first distance is outside a value expected for the first distance. ### Claim 8 (depends on 6) The method of claim 6, further comprising one or more of the following: determining a second distance from a result of a computing operation two working cycles behind and the result of the current working cycle; determining a third distance from the result of a computing operation two working cycles behind and the result of the computing operation one working cycle behind; determining a first difference from a difference between the result of the computing operation one working cycle behind and the result of the current working cycle; determining a second difference from a difference between the result of the computing operation two working cycles behind and the result of the computing operation one working cycle behind. ### Claim 9 (depends on 8) The method of claim 8, wherein the error indication is output when: the second distance is shorter than the first distance; the second distance is shorter than the third distance; and the first difference has a sign which differs from the second difference. ### Claim 10 (depends on 8) The method of claim 8, further comprising: determining a fourth distance from a result of a computing operation three working cycles behind and the result of the computing operation one working cycle behind; determining a fifth distance from the result of the computing operation three working cycles behind and the result of the computing operation two working cycles behind; determining a third difference from a difference between the result of the computing operation three working cycles behind and the result of the computing operation two working cycles behind. ### Claim 11 (depends on 10) The method of claim 10, wherein the error indication is output when: the second distance is shorter than the first distance; the second distance is shorter than the third distance; the fourth distance is shorter than the third distance; the fourth distance is shorter than the fifth distance; the first difference has a sign which differs from the third difference; and the third difference has a sign which differs from the second difference. ### Claim 12 (depends on 1) The method of claim 1, wherein at least one distance is determined for each working cycle according to the comparison scheme. ### Claim 13 (depends on 1) The method of claim 1, wherein at least one distance is determined for every nth working cycle according to the comparison scheme, where n is a natural number. ### Claim 14 A computer program product configured to, when executed by the at least one multicore processor in a control system, cause the control system to perform: calculate a computing operation on a processor core of the multicore processor which is allocated according to a distribution scheme; determine at least one distance between a current result of the computing operation and at least one result of a computing operation at least one working cycle behind within a current working cycle and based on a comparison scheme; output an error indication when at least one distance is outside an expected value; and calculate a subsequent computing operation on a separate processor core of the multicore processor which is allocated according to the distribution scheme. ### Claim 15 (depends on 2) The method of claim 2, wherein an allocation to a first processor core of the multicore processor for a predefinable plurality of working cycles is provided according to the distribution scheme before the allocation is changed to a second processor core of the multicore processor. ### Claim 16 (depends on 15) The method of claim 15, wherein, when the error indication is output, the plurality of working cycles for allocation to the first processor core is increased. ### Claim 17 (depends on 3) The method of claim 3, wherein the computing operations are each allocated to one of at least three processor cores of the multicore processor in a rotating manner. ### Claim 18 (depends on 2) The method of claim 2, wherein a first distance is determined from the previous result of the computing operation of the one working cycle behind and the result of the current working cycle according to the comparison scheme.