# US 2018/0321939 A1 · Processing units having triangular load protocol

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- Number: US 2018/0321939 A1
- Document ID: US20180321939A1
- Status: Published application
- Kind: A1
- Application number: 15/586,937
- Filed: 2017-05-04
- Published: 2018-11-08
- Earliest claimed: 2017-05-04
- Assignees: Futurewei Technologies, Inc.
- Applicants: Futurewei Technologies, Inc.
- Inventors: Alan Gatherer; Sushma Wokhlu; Peter Yan; Ywhpyng Harn; Ashish Rai Shrivastava; Tong Sun; Lee Dobson McFearin
- Web page: https://patentgrep.com/patent/US20180321939A1

## CPC

- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0656: {Data buffering arrangements}
- G06F 3/0673: {Single storage device}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 9/3881: {Arrangements for communication of instructions and data}
- G06F 9/46: Multiprogramming arrangements
- G06F 12/0853: Cache with multiport tag or data arrays
- G06F 12/0884: Parallel mode, e.g. in parallel with main memory or CPU
- G06F 13/16: for access to memory bus (G06F13/28 takes precedence)
- G06F 12/0859: {with reload from main memory}
- G06F 12/0868: Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
- G06F 2212/1008: Correctness of operation, e.g. memory ordering
- G06F 2212/1016: Performance improvement
- G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.

## Claims

### Claim 1

An apparatus for executing a machine instruction, comprising:
master processing logic configured to at least partially decode the machine instruction to determine whether data is needed to execute the machine instruction;
consumer processing logic coupled to the master processing logic; and
storage that is accessible to the consumer processing logic;
wherein the master processing logic is configured to provide to the consumer processing logic at least a portion of the machine instruction;
wherein the master processing logic is configured to send a read request to memory for the data needed, wherein the read request indicates that the data is to be sent from the memory to the storage that is accessible to the consumer processing logic;
wherein the consumer processing logic is configured to access the data from the storage and to execute the machine instruction based on the accessed data.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a first-in, first-out (FIFO) buffer, wherein the master processing logic is further configured to provide the at least a portion of the machine instruction to the FIFO buffer responsive to a determination that the data is needed and that the consumer processing logic is to execute the machine instruction, wherein the consumer processing logic is configured to access the machine instruction from the FIFO buffer.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the FIFO buffer has a depth that is configured to provide a delay such that the data for the machine instruction is in the storage by the time the consumer processing logic accesses the machine instruction from the FIFO buffer.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the read request comprises a destination address.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the read request comprises a destination type.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the storage comprises read storage for storing the data from memory and write storage for storing data to be written from the consumer processing logic to memory.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the consumer processing logic further comprises read storage management logic configured to read a destination address in a read response sent from the memory and store the data to the read storage when the destination address corresponds to an address of the consumer processing logic.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the apparatus further comprises write storage management logic configured to remove data from the write storage after the data has been written to the memory.

### Claim 9 (depends on 6)

The apparatus of claim 6, wherein the apparatus further comprises a hazard logic configured handle hazards between the read storage and write storage.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the master processing logic and the consumer processing logic are in one processor.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein the master processing logic resides on a first semiconductor die and the consumer processing logic resides on a second semiconductor die other than the first semiconductor die.

### Claim 12 (depends on 1)

The apparatus of claim 1, further comprising a clock generation circuitry configured to provide a first clock signal to the master processing logic and a second clock signal to the consumer processing logic, wherein the first clock signal has a frequency different from a frequency of the second clock signal.

### Claim 13

A method of executing a machine instruction, comprising:
fetching, by master processing logic, the machine instruction;
decoding the machine instruction, at least partially, by the master processing logic;
determining, by the master processing logic, that data is needed to execute the machine instruction;
sending, by the master processing logic to a memory, a request to provide the data for executing the machine instruction to storage that is accessible to consumer processing logic;
providing, by the master processing logic, at least a portion of the machine instruction to the consumer processing logic;
receiving, from the memory, the data at the storage; and
executing, by the consumer processing logic, the machine instruction using the data in the storage.

### Claim 14 (depends on 13)

The method of claim 13, wherein the executing, by the consumer processing logic, the machine instruction comprises:
executing the machine instruction after the data for the machine instruction arrives in the storage; and
removing the data from the storage.

### Claim 15 (depends on 13)

The method of claim 13, wherein the providing, by the master processing logic, at least a portion of the machine instruction to the consumer processing logic comprises:
sending the at least a portion of the machine instruction to a first-in first-out (FIFO) buffer that is accessible to the consumer processing logic.

### Claim 16 (depends on 13)

The method of claim 13, wherein sending, by the master processing logic to a memory, a request to provide the data for executing the machine instruction comprises:
adding a destination address of the consumer processing logic to a read request packet.

### Claim 17 (depends on 13)

The method of claim 13, further comprising:
receiving, by the consumer processing logic, a read response packet from the memory; wherein the read response packet comprises a destination address of the consumer processing logic.

### Claim 18 (depends on 17)

The method of claim 17, wherein receiving, from the memory, the data at the storage comprises:
accessing the destination address in the read response packet; and
storing the data in the storage responsive to a determination that the destination address matches an identifier of the consumer processing logic.

### Claim 19

An apparatus for executing an instruction, comprising:
a non-transitory memory storage comprising data;
one or more processors in communication to the memory, wherein the one or more processors comprises master processing logic and at least one consumer processing logic,
wherein the master processing logic at least partially decodes the instruction to determine whether data is needed to execute the instruction; provides at least a portion of the instruction to one of the at least one consumer processing logic; and sends a read request to the memory for the data needed, wherein the read request indicates a destination address to where the data need to be sent;
wherein the at least one consumer processing logic receives a read response from the memory indicating the destination address to where the data need to be sent;
wherein the one of the at least one consumer processing logic receives data from the memory and executes the at least the portion of the instruction when the destination address is corresponding to an address of the one of the at least one consumer processing logic.

### Claim 20 (depends on 19)

The apparatus of claim 19, each of the at least one consumer processing logic further comprises:
a read storage for storing the data from memory;
a write storage for storing data to be written to the memory;
a first-in, first-out (FIFO) buffer that receives the at least a portion of the instruction from the master processing logic.