# US 2018/0321844 A1 · System and method for processing and arbitrating submission and completion queues

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- Number: US 2018/0321844 A1
- Document ID: US20180321844A1
- Status: Published application
- Kind: A1
- Application number: 15/585,717
- Filed: 2017-05-03
- Published: 2018-11-08
- Earliest claimed: 2017-05-03
- Assignees: Western Digital Technologies, Inc.
- Applicants: Western Digital Technologies, Inc.
- Inventors: Shay Benisty
- Web page: https://patentgrep.com/patent/US20180321844A1

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 13/1626: {by reordering requests}
- G06F 13/1642: {with request queuing}
- G06F 13/18: based on priority control (G06F13/1605 takes precedence)
- G06F 13/26: with priority control
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 2213/0026: PCI express
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Systems and methods for processing and arbitrating submission and completion queues are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. The memory device may process the commands based on the determined priority of the command. For example, the memory device may determine a priority for performing the phases after fetching the command. As another example, the memory device may perform the internal command selection based on a priority associated with the command. In this way, commands may be executed based on the priority needs of the memory device or of the host device.

## Claims

### Claim 1

A method for a memory device to process one or more commands, the method comprising:
fetching commands from a plurality of submission queues, a host device causing the commands to be stored in the plurality of submission queues in order for the memory device to process the commands;
determining a priority of the commands; and
after fetching, processing the commands based on the determined priority.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
processing the commands comprises prioritizing the commands for execution; and
prioritizing the commands for execution is based on the determined priority.

### Claim 3 (depends on 2)

The method of claim 2, wherein:
prioritizing the commands for execution comprises command scheduling; and
the command scheduling is based on the determined priority.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
processing the commands comprises the memory device causing indications to be stored in one or more completion queues, a respective indication indicative that a respective command has been executed by the memory device; and
causing the indications to be stored in the one or more completion queues is based on the determined priority.

### Claim 5 (depends on 1)

The method of claim 1, wherein processing the commands comprises the memory device:
causing indications to be stored in one or more completion queues, a respective indication indicative that a respective command has been executed by the memory device; and
generating an interrupt to the host device, the interrupt indicative to the host device that the indications are stored in the one or more completion queues;
wherein generating the interrupt to the host device is based on the determined priority.

### Claim 6 (depends on 1)

The method of claim 1, wherein determining the priority of the commands comprises:
determining a respective submission queue associated with a respective command; and
assigning the priority for the respective command based on a priority of the respective submission queue.

### Claim 7 (depends on 6)

The method of claim 6, wherein:
the plurality of submission queues comprises a first submission queue and a second submission queue;
the first submission queue is assigned a higher priority than the second submission queue; and
processing of the commands fetched from the first submission queue is assigned a higher priority than processing of the commands fetched from the second submission queue.

### Claim 8 (depends on 7)

The method of claim 7, wherein:
the first submission queue comprises an administrative submission queue; and
the second submission queue comprises a non-administrative submission queue.

### Claim 9 (depends on 1)

The method of claim 1, wherein determining the priority of the commands comprises:
determining a command type of a respective command; and
assigning the priority for the respective command based on the command type.

### Claim 10 (depends on 1)

The method of claim 1, wherein determining the priority of the commands comprises:
determining an address associated with a respective command; and
assigning the priority for the respective command based on the determined address.

### Claim 11

A non-volatile memory device comprising:
a non-volatile memory having a plurality of memory cells;
a communication interface configured to communicate with a host device, the memory device to perform one or more actions related to commands fetched from one or more submission queues, the one or more actions comprising actions the memory device performs in processing the fetched commands; and
a controller in communication with the non-volatile memory and the communication interface, the controller configured to:
fetch commands from one or more submission queues;
determine a priority of the fetched commands; and
perform the one or more actions in an order determined based on the priority of the fetched commands.

### Claim 12 (depends on 11)

The non-volatile memory device of claim 11, wherein:
the one or more actions comprises execution of the fetched commands; and
the controller is configured to determine the order of execution of the fetched commands based on the determined priority of the fetched commands.

### Claim 13 (depends on 11)

The non-volatile memory device of claim 11, wherein:
the one or more actions comprises obtaining physical region pages associated with the fetched commands; and
the controller is configured to determine the order of obtaining the physical region pages for the fetched commands based on the determined priority of the fetched commands.

### Claim 14 (depends on 11)

The non-volatile memory device of claim 11, wherein the one or more actions is associated with one or more completion queues.

### Claim 15 (depends on 14)

The non-volatile memory device of claim 14, wherein the one or more actions comprises causing an indication of a command completion to be written to a respective completion queue.

### Claim 16 (depends on 14)

The non-volatile memory device of claim 14, wherein the one or more actions comprises generating an interrupt to the host device to indicate to the host device that an indication of a command completion is written to a respective completion queue.

### Claim 17 (depends on 11)

The non-volatile memory device of claim 11, wherein the controller is configured to determine the priority of the fetched commands by:
determining a respective submission queue associated with a respective command; and
assigning the priority for the respective command based on a priority of the respective submission queue.

### Claim 18 (depends on 11)

The non-volatile memory device of claim 11, wherein the controller is configured to determine the priority of the fetched commands by:
analyzing at least one aspect of the fetched command; and
assigning the priority for the fetched command based on the analysis of the at least one aspect of the fetched command.

### Claim 19 (depends on 18)

The non-volatile memory device of claim 18, wherein the at least one aspect comprises a type of the fetched command.

### Claim 20 (depends on 18)

The non-volatile memory device of claim 18, wherein the at least one aspect comprises a memory address associated with the fetched command.

### Claim 21

A non-volatile memory system comprising:
a non-volatile memory having a plurality of memory cells:
a communication interface configured to communicate with a host device;
means for fetching commands, via the communication interface, from a plurality of submission queues, the host device causing the commands to be stored in the plurality of submission queues;
means for determining a priority of the commands; and
after fetching, means for processing the commands based on the determined priority.

### Claim 22 (depends on 21)

The non-volatile memory system of claim 21, wherein the means for determining the priority of the commands is based on a respective submission queue from which a respective command was fetched.