# US 2018/0321309 A1 · Shadow access port method and apparatus

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- Number: US 2018/0321309 A1
- Document ID: US20180321309A1
- Status: Published application
- Kind: A1
- Application number: 16/037,649
- Filed: 2018-07-17
- Published: 2018-11-08
- Earliest claimed: 2008-03-28
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20180321309A1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318544: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)}
- G01R 31/318555: {Control logic}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

## Claims

### Claim 1

An integrated circuit comprising:
(a) a TCK lead, a TMS lead, a TDI lead, and a TDO lead;
(b) a test access port circuit having a TCK input coupled to the TCK lead, a TMS input coupled to the TMS lead, a TDI input coupled to the TDI lead, a TDO output coupled to the TDO lead, a data register and an instruction register that are coupled to the TDI input and that are selectively coupled to the TDO output, and a state machine that is coupled to the TCK input, the TMS input, the data register and the instruction register, the state machine changing states upon a rising edge of a clock signal on the TCK lead;
(c) an inverter having an input coupled to the TCK lead and an output; and
(d) a shadow access port circuit having:
a TCK input coupled to the output of the inverter,
a TMS input coupled to the TMS lead,
a TDI input coupled to the TDI lead,
a TDO output coupled to the TDO lead,
multiplexer circuitry having a data register input, an instruction register input, a TDO output coupled to the TDO lead, and a control input;
a data register having an input coupled to the TDI input, an output coupled to the data register input, and a control input,
an instruction register having an input coupled to the TDI input, an output coupled to the instruction register input, and a control input, and
a state machine that is coupled to the TCK input, the TMS input, and control outputs that are coupled to the control inputs of the multiplexer circuitry, the data register, and the instruction register, the state machine changing states upon a falling edge of a clock signal on the TCK lead.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which the state machine of the test access port circuit steps through the states of SELECT-DR, CAPTURE-DR, SHIFT-DR, EXIT1-DR, PAUSE-DR, EXIT2-DR, and UPDATE-DR.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which the state machine of the shadow access port circuit steps through the states of SELECT-DR, CAPTURE-DR, SHIFT-DR, and UPDATE-DR without shifting through states of EXIT1-DR, PAUSE-DR, or EXIT2-DR.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 in which the state machines of both access port circuits have a RESET state and an IDLE state.