# US 2018/0321306 A1 · Dynamic scan chain reconfiguration in an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0321306 A1 - Document ID: US20180321306A1 - Status: Published application - Kind: A1 - Application number: 15/589,644 - Filed: 2017-05-08 - Published: 2018-11-08 - Earliest claimed: 2017-05-08 - Assignees: Xilinx, Inc. - Applicants: Xilinx, Inc. - Inventors: Partho Tapan Chaudhuri - Web page: https://patentgrep.com/patent/US20180321306A1 ## CPC - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G01R 31/31723: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)} - G01R 31/31724: {Test controller, e.g. BIST state machine (for scan test G01R31/318555)} - G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals} - G01R 31/318544: {Scanning methods, algorithms and patterns (G01R31/3183 takes precedence)} - G01R 31/318558: {Addressing or selecting of subparts of the device under test} - G01R 31/3187: Built-in tests - G06F 11/267: Reconfiguring circuits for testing, e.g. LSSD, partitioning - G06F 11/27: Built-in tests - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An example test circuit for an integrated circuit (IC) having a plurality of scan chains includes: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains. ## Claims ### Claim 1 A test circuit for an integrated circuit (IC) having a plurality of scan chains, the test circuit comprising: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains. ### Claim 2 (depends on 1) The test circuit of claim 1, wherein the first circuit comprises logic built-in self-test (LBIST) circuitry, and wherein the second circuit comprises scan compressor/decompressor circuitry. ### Claim 3 (depends on 2) The test circuit of claim 2, wherein the scan compressor/decompressor circuitry provides an interface between automated test equipment (ATE) and the scan chain router. ### Claim 4 (depends on 1) The test circuit of claim 1, wherein each of the plurality of scan chains comprises a plurality of sequentially coupled flip-flops disposed in core logic of the IC. ### Claim 5 (depends on 1) The test circuit of claim 1, wherein the scan chain router comprises: a bypass router circuit coupled between the first circuit and the plurality of scan chains; and a chain concatenation circuit coupled between the second circuit and the plurality of scan chains. ### Claim 6 (depends on 5) The test circuit of claim 5, wherein the first circuit includes an output having a plurality of output signals and an input having a plurality of input signals, and wherein the bypass router circuit is configured to couple each of the plurality of output signals to a respective one of the plurality of scan chains and to receive each of the plurality of input signals from a respective one of the plurality of scan chains. ### Claim 7 (depends on 5) The test circuit of claim 5, wherein the second circuit includes an output having one or more output signals and an input having one or more input signals, and wherein the chain concatenation circuit is configured to couple each of the one or more output signals to a respective one of the one of more concatenated scan chains and to receive each of the one or more input signals from a respective one or more of the concatenated scan chains. ### Claim 8 (depends on 1) The test circuit of claim 1, wherein the second circuit comprises: a decompressor that includes the output having the one or more output signals; and a compressor that includes the input having the one or more input signals. ### Claim 9 An integrated circuit (IC), comprising: a plurality of scan chains; and test circuitry coupled to the plurality of scan chains, the test circuitry including: a first circuit and a second circuit; and a scan chain router coupled between the first circuit and the plurality of scan chains and coupled between the second circuit and the plurality of scan chains, the scan chain router responsive to an enable signal to: (1) couple the first circuit to each of the plurality of scan chains; or (2) couple the second circuit to one or more concatenated scan chains, where each concatenated scan chain includes a concatenation of two or more of the plurality of scan chains. ### Claim 10 (depends on 9) The IC of claim 9, wherein the first circuit comprises logic built-in self-test (LBIST) circuitry, and wherein the second circuit comprises scan compressor/decompressor circuitry. ### Claim 11 (depends on 10) The IC of claim 10, wherein the scan compressor/decompressor circuitry provides an interface between automated test equipment (ATE) and the scan chain router. ### Claim 12 (depends on 9) The IC of claim 9, wherein each of the plurality of scan chains comprises a plurality of sequentially coupled flip-flops disposed in core logic of the IC. ### Claim 13 (depends on 9) The IC of claim 9, wherein the scan chain router comprises: a bypass router circuit coupled between the first circuit and the plurality of scan chains; and a chain concatenation circuit coupled between the second circuit and the plurality of scan chains. ### Claim 14 (depends on 13) The IC of claim 13, wherein the first circuit includes an output having a plurality of output signals and an input having a plurality of input signals, and wherein the bypass router circuit is configured to couple each of the plurality of output signals to a respective one of the plurality of scan chains and to receive each of the plurality of input signals from a respective one of the plurality of scan chains. ### Claim 15 (depends on 13) The IC of claim 13, wherein the second circuit includes an output having one or more output signals and an input having one or more input signals, and wherein the chain concatenation circuit is configured to couple each of the one or more output signals to a respective one of the one of more concatenated scan chains and to receive each of the one or more input signals from a respective one or more of the concatenated scan chains. ### Claim 16 (depends on 9) The IC of claim 9, wherein the second circuit comprises: a decompressor that includes the output having the one or more output signals; and a compressor that includes the input having the one or more input signals. ### Claim 17 A method of testing an integrated circuit (IC) having a plurality of scan chains, the method comprising: concatenating the plurality of scan chains into one or more concatenated scan chains, each concatenated scan chain including a concatenation of two or more of the plurality of scan chains; receiving one or more test signals from automatic test equipment (ATE); decompressing the one or more test signals; coupling each of the one or more test signals to a respective one of the concatenated scan chains; and coupling an output of each of the one or more concatenated scan chains to the ATE. ### Claim 18 (depends on 17) The method of claim 17, further comprising: controlling an enable signal coupled to a scan chain router to perform the step of concatenating. ### Claim 19 (depends on 18) The method of claim 18, wherein the step of controlling comprises: enabling a chain concatenation circuit to perform the step of concatenating; and disabling a bypass router circuit; ### Claim 20 (depends on 19) The method of claim 19, wherein the bypass router circuit is coupled between a logic built-in self-test (LBIST) circuit and the plurality of scan chains.