Back to results
US 2018/0315852 A1Published application
Strain gated transistors and method
AssigneeThe Regents of the University of California
InventorsCengiz S. Ozkan, Mihrimah Ozkan, Yu Chai
Life of this patent
Estimating the term…
Abstract
A strain gated transistor and associated methods are shown. In one example, a transistor channel region includes a metal dichalcogen layer that is stressed to improve electrical properties of the transistor.
Claims15
A semiconductor device, comprising:
- a first source/drain region, and a second source/drain region;
- a transition metal dichalcogenide channel region coupled between the first source/drain region and the second source/drain region;
- a gate located adjacent to the channel region and separated therefrom by a gate dielectric;
- and
- a strain layer coupled adjacent to the channel region to provide axial strain in the transition metal dichalcogenide channel region.
2 more elements
A method of forming a semiconductor device, comprising:
- forming a transition metal dichalcogenide layer on a substrate;
- removing a portion of the transition metal dichalcogenide layer to form a channel region;
- forming a first source/drain region at a first end of the channel region, and a second source/drain region at a second end of the channel region;
- forming a gate dielectric on the channel region;
- forming a gate on the gate dielectric;
- coupling a strain layer adjacent to the channel region to provide axial strain in the channel region.
3 more elements
Dependencies are inferred from the claim text.