Fine resolution high speed linear delay element
AssigneeCiena Corporation
InventorsMahdi Parvizi, Sadok Aouini, Naim Ben-Hamida
Life of this patent
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Abstract
A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.
Claims20
A controlled transconductance circuit (CTC), comprising:
- a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal;
- a biasing circuit element connected between the transistor source terminal and a CTC source terminal;
- a variable capacitor connected between the transistor source terminal and a constant voltage terminal, wherein the constant voltage terminal is adapted to receive a constant voltage;
- and
- a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.
A controlled delay circuit (CDC), comprising:
- a controlled transconductance circuit (CTC) comprising
- a CTC drain terminal and a CTC source terminal that are adapted to conduct a current of the CTC,
- a CTC gate terminal adapted to receive an input voltage signal referenced with respect to the CTC source terminal, wherein the input voltage signal modulates the current based on a transconductance of the CTC, and
- a CTC control terminal adapted to control the transconductance based on a digital bit value applied to the CTC control terminal;
- and
- an output delay capacitor coupled between the CTC drain terminal and a first constant voltage terminal of the CDC,
- wherein the first constant voltage terminal is adapted to receive a first constant voltage, and
- wherein the transconductance and the output delay capacitor collectively define a signal delay of the input voltage signal from the CTC gate terminal to the CTC drain terminal.
A method for a controlled delay circuit (CDC), comprising:
- applying a control signal to a control terminal of the CDC;
- adjusting, based at least on the control signal, a transconductance of the CDC;
- receiving, at a gate terminal of the CDC, an input voltage signal;
- and
- generating, subsequent to receiving the input voltage signal, an output signal at a drain terminal of the CDC with a signal delay,
- wherein the signal delay is proportional to a ratio between a load capacitance of the CDC and the transconductance.
Dependencies are inferred from the claim text.