# US 2018/0300237 A1 · Method for access to all the cells of a memory area for purposes of writing or reading data blocks in said cells > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2018/0300237 A1 - Document ID: US20180300237A1 - Status: Published application - Kind: A1 - Application number: 16/015,779 - Filed: 2018-06-22 - Published: 2018-10-18 - Earliest claimed: 2013-01-07 - Assignees: Morpho - Applicants: Morpho - Inventors: Ahmadou SERE; Frédéric BOULET - Web page: https://patentgrep.com/patent/US20180300237A1 ## CPC - G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)} - G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)} - G06F 7/582: {Pseudo-random number generators} - G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)} - G06F 2212/251: Local memory within processor subsystem - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for access to all cells in a memory area for purposes of writing or reading data blocks in the cells may include, for each access time (Ti with i=0 to N) to the cells in the memory area to be accessed, a process of determining the address (ADRj, with j=0 to N) of the cell of the memory area to be accessed at the access time (Ti), an address (ADRj) determined for an access time Ti not being once again determined for another access time (Tk, k≠j). The process of determining each address (ADRj) may be a pseudorandom process. The method may be used, for example, in any type of card, chip card, SIM card, etc., which includes a processing unit, such as a microcontroller, for manipulating cryptographic data serving to identify and/or authenticate a user of such a card. ## Claims ### Claim 1 An access method to access to cells in a memory area of a card for purposes of writing or reading data blocks in said cells, wherein said method comprises: for each access time to said cells in said memory area to be accessed, performing a process of address determining an address of a cell of the memory area to be accessed at said access time, the address determined for an access time not being once again determined for another access time, the address determination process comprising: randomly determining a random bit which can thus take either a first value or a second value; and testing the value taken by said random bit that switches said process either to: (1) determining an index as being equal to the value of a first index, followed by incrementing a unit of said first index, or (2) determining said index as being equal to the value of a second index, followed by decrementing a unit of said second index, the value of said index being the value of said address of the cell of the memory area to be accessed at said access time. ### Claim 2 (depends on 1) The access method according to claim 1, further comprising applying to the index IDX a bitwise exclusive OR operation with a random number before the method of determining addresses of the memory area is launched. ### Claim 3 (depends on 1) The access method according to claim 1, wherein said randomly determining comprises randomly choosing the value of said random bit. ### Claim 4 (depends on 1) The access method according to claim 1, wherein said randomly determining comprises extracting from a register the bit corresponding to the rank of the access time in question, said register storing a number previously determined pseudorandomly. ### Claim 5 (depends on 4) The access method according to claim 4, wherein the number stored in said register was determined during a previous instance of implementation of said randomly determining comprising randomly choosing the value of said random bit by concatenation of all the random bits so that the random bit determined during the first instance for an access time of rank is stored in the bit of said register the weight of which is equal to said rank. ### Claim 6 (depends on 1) The access method according to claim 1, wherein the access time is defined from i 0 to N, and wherein, said memory area being of size N+1, the initial value of the first index is between 0 and N and the initial value of the second index is equal to the initial value of the first index to which the size of said memory area minus one is added. ### Claim 7 (depends on 6) The access method according claim 6, wherein the initial value of the first index is determined randomly or pseudorandomly. ### Claim 8 (depends on 1) The access method according to claim 1, further comprising determining the value of a random number, and in that said determination process further comprises, after determination of the value of the index for the access time, a step of applying to the index thus determined a bitwise exclusive OR logic operation with said random number, the value resulting from said operation being the value of the address for access to the cell of the memory area to be accessed at said access time. ### Claim 9 (depends on 1) The access method according to claim 1, further comprising determining the value of a random number, wherein said address determination process further comprises, after determination of the value of the index for the access time, calculating a mask value, applying to said value of the random number a bitwise logic AND operation with said mask, and applying to the index determined for the access time in question a bitwise exclusive OR logic operation with the result of said logic AND operation, the value resulting from the exclusive OR operation being the value of the address for access to the cell of the memory area to be accessed at said access time. ### Claim 10 (depends on 9) The access method according to claim 9, wherein said step (E71) of calculating a mask value comprises: positioning the most significant bit of said mask at zero and then, for each bit of weight i successively taking the values from S−1 to 1, S being the size in number of bits of the variables used for the logic operations, applying, to the bit of weight i of the determined index, an exclusive OR logic operation with the bit of weight i of the size of said memory area, applying to said result of said exclusive OR logic operation, a logic OR operation with the bit of weight i of the mask, positioning the bit of weight i−1 of the mask at the value of the result of said logic OR operation. ### Claim 11 (depends on 6) The access method according to claim 6, further comprising shifting the addresses by adding or subtracting, to or from the value of the index, wherein the value comprises previously drawn randomly. ### Claim 12 (depends on 1) A device of a chip card type comprising a processor configured to access a memory, either in writing or reading, wherein said processor is configured to implement the access method according to claim 1. ### Claim 13 (depends on 1) A program implemented on a memory medium, configured to be used with a processor and comprising instructions for implementing the access method according to claim 1. ### Claim 14 An access method to access to cells in a memory area of a card for purposes of writing or reading data blocks in said cells, wherein said method comprises: for each access time to said cells in said memory area to be accessed, performing an process of address determining an address of a cell of the memory area to be accessed at said access time, the address determined for an access time not being once again determined for another access time; and determining the value of a random number; wherein said address determination process comprises: randomly determining a random bit which can thus take either a first value or a second value; and calculating a mask value and applying to said value of the random number a bitwise logic AND operation with said mask, and applying to an index determined for the access time in question a bitwise exclusive OR logic operation with a result of said logic AND operation, the value resulting from the exclusive OR operation being the value of the address for access to the cell of the memory area to be accessed at said access time. ### Claim 15 An access method to access to cells in a memory area of a card for purposes of writing or reading data blocks in said cells, wherein said method comprises: for each access time to said cells in said memory area to be accessed, performing a process of address determining an address of a cell of the memory area to be accessed at said access time, the address determined for an access time not being once again determined for another access time, the address determination process comprising: randomly determining a random bit which can thus take either a first value or a second value; testing the value taken by said random bit that switches said process either to: (1) determining a value index as being equal to the value of a first index, followed by incrementing a unit of said first index, or (2) determining said value index as being equal to the value of a second index, followed by decrementing a unit of said second index, the value of said value index being the value of said address of the cell of the memory area to be accessed at said access time; and applying to the value index a bitwise exclusive OR operation with a random number before the address determination process.